Welcome to our RU-vid channel for BYU's Computing Bootcamp! This channel is dedicated to helping you build important skills with coding and computers. Videos are comprised of Zoom recordings from the lecture series the BYU Electrical and Computer Engineering department does for their research program IMMERSE each summer.
I might use a Mecano anaolgy here. If we pretend for a second that Mecano was all there was: A CPU would be like a tape-based music box (built out of Mecano... yeh, bear with it). It's all welded together, so you can't change the mechanism, and provided you feed it the right punched tape it will make great-sounding soft music. An ASIC would be a special music box, maybe it has less range, maybe it has a few more harps, but the music is on a steel drum. Again, all the Mecano bits are welded together, so can't be changed. It plays that one song and it plays it really well. An FPGA, in contrast, is just a box of Mecano parts (sub-assemblies really). Go build what ever you want ;)
Hmm... wouldn't it be sensible for a write-once offering to have a rewritable counterpart for testing purposes? Especially when they come with a $100k price tag...
Nice tutorial.. Can you tell me which debugger are you using for programming and debugging in this video? Which one is good to use for multiple CPU's and FPGA core debugging?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
