I am an Associate Professor of Computer Science at Southwestern University in Georgetown, TX. The primary purpose of this channel is to host instructional videos that I use for reverse teaching, also known as the flipped classroom model. However, I hope these videos will also be useful to other students and educators.
Lets get lost tonight, you could be my black Kate Moss tonight, play secretary I'm the boss tonight, and you don't give a f*ck what they all say right. 😂
Thanks for nice explanation. I have doubt about if both CPUs issue write request to the same data location, then how it is resolved? As it seems to be the race condition then do I need to synchronize this scenario or what?
It absolutely would be a race condition, and you would need to assure correct behavior with synchronization at the level of code. However, this coherence protocol would assure that any subsequent reads make sense, meaning that you can't do two simultaneous reads and get different values.
I missed this lecture and was totally clueless when we had to manually calculate a frame check sequence. This is exactly what I needed, and probably explained more clearly than the professor too! Thank you
When CPU 1 performs the Read operation will it fetch the new data which is modified by CPU 2 or it will get the old data that was there before CPU 2 modified it?
If a cache entry enters an Invalid State, then its contents will never be written back to memory. A cache line enters an Invalid state when the shared data is written/modified within another cache. So, the cache contents that eventually get written back to memory will come from a Modified or Shared cache line that corresponds to the same one that was Invalidated in some other cache.
Here is the values for the parameters in the equation, for who still cannot link up the action demonstration and the equation: 7:08 Given: gamma = 1, alpha = 0.5, The cost refers to r_action = -0.04 Let s = (bottom left corner) denoted as [[0,0,0,0], [0,0,0,0], [1,0,0,0]) (as long as you can identify the location) a = UP Q(bottom left, , UP) = 0 + 0.5(-0.04 + 1*0 -0) = -0.02
I've seen a lot of cache videos, but none of them explained how the tags worked. This is the first video that very clearly explains direct mapping. Thanks!
Every opcode has support for specific addressing modes. Sometimes the addressing is determined by the opcode itself, and there are even cases when a seemingly identical assembly instruction (same mnemonic) will translate to different opcodes. However, some instruction sets have an extra portion of the instruction format that specifies the addressing mode.
@@JacobSchrum so when the operands need more bits allocated for allowing more memory addresses then you use the addressing mode right? i was always wondering because on some diagrams for binary code ill see that multiple bits are used for the addressing mode each bit would represent direct or indirect addressing right?is there a certain combination of bits that would show what addressing mode its using like for instance would there be a certain sequence of binary numbers that would imply Indirect addressing Mode, or Indexed addressing mode
You haven't shown how base 4 systems work. I would be interested in seeing base 4 truth tables and logic circuits, flip-flops is where it's at. Have you ever used Forth? Chuck Moore is a genius. Forth, for rapid development, is 2600% faster than C, based on a comparable project. In C, 6 Engineers 1 year. In Forth, 2 Engineers 2 weeks.
At 2:15, won't we have a Frame 2 re-transmission by the sender because the receiver only sends an ACK2 (RR 2), and the sender goes like "okay, the receiver got 0, 1; but he missed a 2". It then shrinks its window, removing the 0 and 1, BUT it still transmits the Frame 2 (F2) that you did not do at 2:20? Also, do we really have the "reject" messages that are sent by the receiver, or do we just have a time-out on the sender side that makes the sender to repeat the transmissions that are in it's current window? I ask this because a few other sources (I am not very sure I believe them, but it is good to clarify I think) do not mention these "reject" messages
The sender knows that it already sent Frame 2, and the RR 2 doesn't mean that the transmission of Frame 2 failed, merely that the receiver has not acknowledged it yet. From the sender's perspective, it assumes that RR 2 was sent while its own Frame 2 message was enroute, and until it has evidence to the contrary, it will assume that Frame 2 message could still have been received. If there is a time-out, then the sender will eventually check to see what is going on, but if the receiver rejects a frame as soon as it sees a gap, it can likely get a quicker response, and possibly spare the sender from transmitting a lot of data that will be discarded anyway.
@@JacobSchrumah okay, thanks! This is a bit different than how I have been taught. Could you please also let me know about: 1) the "reject" messages by the receiver? I have not come across such messages specifically for Go-Back-N, only for Selective Repeat. But I can understand the logic behind it. 2) I have been told that there aren't any NAK's in GBN, but that the "time-out" is the only event in which retransmissions can occur, aiding the receiver in getting those lost frames. Even the "poll" message that you mentioned that the sender has the capability to send. I have not come across those. This is making me even more confused because, everything you say also makes logical sense. Of-course I understand that I am newbie, and really want to know the 'standard' way. I would really appreciate if you have a great resource that I can rely on to study this. 3) Does the sender, in GBN, have logic involved in it's side that allows it to keep track of what are the ACK'ed, UNACK'ed, can-transmit packets in it's window? Because when you mention at 2:15 that the sender just sends the frame 3 after the RR2, it makes me believe that there is some state saving going on the sender side to keep this information. Thanks a ton for such a quick response, I really appreciate it! You are a fantastic source to learn Computer Science from :)
Thanks for this. My professor's a cheapskate and only went over the easiest example of RR where the arrival time of all jobs/processes was 0 but never went into examples where they weren't. Very grateful.
