Hi there Phil , can you make some Motor controlling oriented videos for servos and AC or BLDC , that would be a great knowledge source provided it's your methodology we are speaking of!
Another great video-thank you! Could you share some tips on placing test points and your approach to testing PCBs? I would really appreciate learning more about your process.
Excellent video! I hadn't realized there was so much nuance to these tiny capacitors. I learned something new today. Thank you so much for sharing this!
Why is it a problem to use ground vias under the chip? Is it just that doing so means you may not have "enough" vias, or a problem with heat, or ...? And to keep solder out of those vias, would it work to put solder mask over the vias, so long as most of the thermal pad was bare, or would that interfere with contact?
Doesn't the length of the trace (L) given affect the results? It gave you a very small value but you went over that distance and you used different trace lengths to connect the components. Just curious and new to this
Thank you Phill for your guidance.I have just started out in the Embedded sector and several topics seems quite less daunting with your explanation.Keep up the great work!!!
Thank you so much for producing this, great overview over the essentials of high speed digital design. i still have a question though: when reverse engineering high speed digital circuitry i often found coplanar waveguides instead of microstrip traces. i always thought that was only for RF circuits? When and where should i use coplanar waveguides in my high speed digital pcbs over microstrips? the use of coplanar waveguides is really confusing to me here... i mean the actual frequency isn't that high, only the fft of the edges contain very high frequency components. I don't see a need for coplanar waveguides here? Is it for minimising crosstalk when you can't abide by the 3H rule maybe? Or as an alternate return path on sig gnd pwr sig stackup to avoid long high impedance vias?
Do you really need a whole power layer on quadro board since you make it a reference layer for layer 4 and return path for HF currents will mainly be through decoupling caps, making needs for adjusting return currents?
Hello Phil, Thanks a lot for your videos, they have been always been great companion and help in my study and later work. Still get excited about every and each new design of you. I have also noticed the esthetics are incredibly beautiful, the designs look pretty cool and pieces of art. As a side note could you please share with us how do you do this gradual Copper to power pins? It seems not manually done but sort of systemically as if using tool in altium. Thanks again for offering your work and explanations for us to learn from.
Hi Phil, I'm trying to design a PCB using a STM32U535 controller that's going to be powered by an external battery. It's basically a data logger. I'm kinda confused on how to setup the pins for the ucontroller as most of your videos show cases USB powered systems. Also I'm using Kicad. Do you have any suggestions?
Hi Phil, Bit niche but would you ever consider doing a video on ultra high current e.g. 200A continuous PCB design say for example a power converter? Methods of carrying current and how to interface with MOSFETS? Thanks as always Doron
Hi, I have a question regarding the buck converter part. The board I'm currently working on doesn't have much space on it, what packages for the components do you recommend? Namely, how small can I go? Thanks
I know I'm posting a lot of comments here, sorry, but could you perhaps do a video on how you personally configure Altium, and what QoL features you're commonly using? I keep spotting little details in your videos (e.g. when you're routing, it's showing a kind of "fog of war" for where your traces would violate clearance DRC) that I'm not seeing when using Altium myself.
That hint of tiredness in your voice when you said "vendors like to make their own package types" is something I feel in my bones. I've been digging into DrMOS parts (driver-integrated MOSFETs) and some of their pad layouts look like a box of pads that fell down the stairs. They frequently call them "QFN" but they're really LGA. The mechanical drawings are practically arcane heiroglyphs. I occasionally want to write "BE NOT AFRAID" next to them.
Hey Phil I love your videos. Honestly the only thing I can think of you improving is uploading in 4K just so that some of the text is clearer, otherwise you are so helpful thank you !
Hi Phil, good video! I was just wondering, since I am just a student I don't have that much experience writing such drivers specifically for this type of application. For a schoop project I designed and assembled a board similar to yours and am having some trouble understanding the 'Framework'. Could you maybe share the code or create a video detailing it? Thanks again.
Excellent presentation! I typically design the power layout first. I really like your concept of "intelligent compromise". On some of my designs it felt more like a "hail Mary", with performance checks done soon after the design is working. 1206 caps can be chosen at times, to get around some routing problems.
How to know how many layers are required to a pcb before start the routing of any pcb(for example: whether it requires 2layer or 4 layer or any other layer)
I have designed a pcb using esp32, motor driver,buckconverter,pi filte, and,usb_c. I had a lot of doubts while designing it but after watching this video all doubts were cleared.And also I have enrolled in your paid courses and these courses are amazing.Thank you so much sir.
Another excellent video Phil. One thing that wasn't mentioned (or that I missed) was via tenting and/or via plugging. This is helpfull for clearence and for situations like in 27:42
Hey Phil. I'm always thinking should I put via-s between decoupling capacitor and LQFP/QFN package or first to capacitor and then via down. I have used mostly first to capacitor and then via down. Would be nice video. As I understand when I have power plane then via down directly from LQFP/QFN would be better.
Yeah, it really depends on your PCB stack-up and routing. Definitely worth a whole video I'm currently planning for on decoupling incl. some tests/measurements.
@@PhilsLab I usually do 4 layers and signal-gnd-gnd-signal. If I can't route power on first or bottom layer(happens a lot) I just route power or use power planes on third layer.
Two more tips I picked up from designing mil/aero RF boards 1. Grounded coplanar waveguide is extremely useful for tuning RF amplifiers. Just scrape away soldermask to add shunt tuning components to GND. 2. Another tip for tuning. If you require an L or C, two in parallel will decrease parasitic inductance and possibly improve performance. For example, if you need a 4 pF shunt cap, get two 8 pF and butt them end to end with them meeting at your trace. Of course, they need really low impedance connections (i.e. via in pad) to a GND plane for this to work well.
Thanks for watching! Coincidentally, some demo boards just came in with various antenna types that I'll be showing tuning methods for in an upcoming video!
A few more QFN tips - For lower-speed micros, or other chips where the centre pad is not needed for thermal or RF reasons, you can often omit it, freeing up space to route under the chip - especially useful for 2 layer PCBs. , but check what the datasheet says about how to connect the pad. I do this all the time with PICs (8 & 32 bit) and never had any issues. You ideally want at least 0.5mm of pad length outside of the QFN package outline - this makes inspection and rework much easier - you can even drag-solder for prototyping ( assuming the centre-pad doesn't need soldering). You need a tip with sharp corners to get right down into the pad/lead junction - I like the Thermaltronics M7DS525, which has sharper corners than the Metcal equivalent SMTC1147. If you will need to be prototyping and need to solder the centre pad, leave a cutout in the bottom-side resist - this allows direct heating with a soldering iron, e.g. to reflow paste to solder the centre pad if you don't want to use hot air
On the topic of vias in thermal pads (20:20): -Vias can be filled with various compounds, such as solder resist, epoxy, or copper paste, and then plated over, this process eliminates the risk of solder flowing down the via barrel (using copper paste also improves the thermal conductivity of the via), JLCPCB offers epoxy filling with or without plating as a standard feature on PCBs with six or more layers. However, copper paste filling is significantly more expensive. -Plugged vias without plating tend to create significant solder voids at the PCB-IC interface and should be avoided (see X-ray images in [1]). -Tented vias on the opposite side of the board result in better solder joints with fewer voids, although air can become trapped in the via barrel. This method typically incurs no additional cost. -Smaller drill sizes (less than 0.3 mm) reduce the likelihood of solder flowing down the barrel, but they are generally more expensive. Ultimately, the number, size, and filling type of thermal vias depend on your budget and risk tolerance. Personally, I have used 0.35 mm vias (with no tenting on the other side) on the pad of a D2PAK with hatched solder paste pattern and did not observe any solder wicking issues. Source: [1] SLUA271C - QFN and SON PCB Attachment - Texas Instruments
It's a good design practice to balance the amount of copper on all layers. If your stackup is not symmetric with respect to copper distribution per layer, it can cause the PCB to warp during reflow. Thus it is easy to just fill in the remaining space with GND so that all layers have approximately an equal amount of copper. You have to ensure GND has the appropriate clearance to any high voltage or high speed digital traces (just to give 2 examples), but for most applications it's fine.
The breaking away of the signal traces is something I didn't know. I have been putting them together. After watching your crosstalk video for differential pairs a while ago, I started thinking differently about signal traces.
