am stuck i various projects yet gathering too many docs from YT' and doing it myself where in some areas am stuck and not able to move further. You may also upload some video of calculating components values for circuit designing. Designing circuits for various fields or interest or requirements which are not regular like solar toys, AC-DC inverters, LED disco lights. I felt u shud be sounding great in Electronics. So I thought of gripping ur hand for my individual growth (little selfishness :) ).
Very nicely explained. It'd be veryyyy good if sample or model circuits given in detail with schematic as part 1, 2, .... for the individual segments. Please think abt it.
Excellent explanation. I have always wondered how increasing latency will increase performance and how increasing reg can reduce Pd. This helped with that
Thank you for this wonderful video ma'am! Your explanations were in-depth and extensive! I have a few questions regarding the shorting NMOS, and I will greatly appreciate if you can address those. 1) You gave the reason behind the shorting transistor as preventing any input change from affecting the Sense Amplifier output during Evaluation Phase. I am curious to know a bit more about this failure case. I think that in reality, the Sense Amplifier inputs should not change during Evaluation since that will amount to Hold failure. The input path should be sufficiently delayed to not change its state while the clock is HIGH. So, in my opinion, the design itself should ensure that the Sense Amplifier inputs do not change during Evaluation Phase, and as a result we should not require this shorting NMOS. Can you please share some situation where this input change can occur during Evaluation phase without violating the input Hold Time? 2) I think that having this shorting NMOS actually slows down the Sense Amplifier Response Time and can also be a reason behind a potential failure of this Sense Amplifier. This is because this shorting NMOS is always ON due to which when IN=HIGH, the source of M6 (node L4) will also see GND potential through M4 and M2, since node L4 will be following node L3. In this situation, the only cause behind a differential voltage between nodes L3 and L4 will be the extra delay that M4 will provide for GND potential to travel to node L4. This single NMOS delay is all we have to create a differential. And because of this small window that the Sense Amplifier gets to differentiate between its two arms, it will take more time to resolve the differential. Also, in another scenario, due to mismatch, if M5 becomes weaker than M6 on Silicon, then we may actually approach a zone of metastability of the Sense Amplifier where it may not be able to resolve the input differential. Can you please give your opinion on my observation and correct me where I may be wrong? 3) Under the circumstances where the inputs toggle state during the Evaluation Phase, how can we ensure that the Sense Amplifier will still resolve in the opposite direction because now the source of M6 (node L4) will be directly at GND while the source of M5 (node L3) will see a one NMOS latency through M4, making the Sense Amplifier skewed in the direction of resolving the new state of IN=LOW. So, even having this shorting NMOS is not guaranteeing that we will be able to resolve IN=HIGH state after IN has toggled to IN=LOW, since IN may toggle to LOW immediately after going HIGH. Can you please give your opinion on my observation and correct me where I may be wrong? I request you to please address my questions, for which I will be extremely grateful to you!
Awesome mam, by the first time I am big fan of yours what a great explanation mam. Also mam can you share ppt if possible it can really help us learn and revise the concepts.\
mam ur lecture is nice....plz put a video for all the topics based on the anna university syllabus i didnt see the topics such schmitt trigger, monostable,astable, and timing classification in the 4th unit
