Is stuck at non-controlling value at gates is a 3rd rule.. In slide is written under rule number 2 of EFC rules

Thank you for making such detailed series sir. I reviewed your lectures and got employed for a DFT position.

Hello Professor, since yesterday all your videos got shuffeled in the playlist(It's not in order), can you please change that.

Hi professor why test coverage will be reduced if we go for high compression ratio?

Thank you sir ❤ from India

saaor caan yuuu pleez speenk ingeezz

FFT: scan flipflop is added to control "AND gate to 1" & "OR gate to 0" , Mux is required (with TestMode)

40181 Zita Fall

It is an algorithm for single path/multiple path sensitization with new nomenclature -D- & -D'- (D cubes), Singular cubes etc., correct me.

FFT: Q1. Problem with Multiple path sensitization is that we cannot find a specific path that causes faulty output; rather, we will have multiple paths. correct me, I am confused

6:09 for 011,101 wired AND output is 1 not 0, please anyone point out if am wrong

TE 必讀

Nice overview

Appreciate~ It is a good overview.

Nice Video. The examples are really great. Thank you.

Kindly suggest some good text books

At 10:10 In the normal mode, there is only capture function and hence whatever the fault is stuck at, the flip flop is going to capture only that value. Hence it is difficult to detect stuck at fault in normal mode.

老师讲的真好

Very good explanation.. thank you soo much for sharing 🙂

35:40 😀😀

Thank you for every video

where is clock ir, clock dr, update clock coming?

so confusing slide and explanation.

On launch on shift during str test we are not making any transition from 0 to 1 then how you are testing that pin

Does anyone has the answer and explanation for the final last quiz FFT ?

In 13:30 is it possible to test with 16 patterns in total (instead of 20 , we can parallel lines 17-20 to 13-16 , because those segment are independent)?

why scan testing for logic is not applicable to memory?

Still confused in +ve & -ve FF together...can u explain with more detailed example (assuming I will never get reply from 6 yr old video)

How are no coupling faults detected in mats algorithm?

Does this work for any M(x) when I try it it doesn't?

This is by far the best DFT/ATPG lesson in RU-vid. I hope you keep these videos in RU-vid for all the future IC engineers to watch. Thank you very much.

Your videos are extremely helpful for new test engineers like me. Thank you so much for sharing your knowledge in such a clear manner

李老師牛逼

@31:00 as we backtrack for G7 to be1 both input should be 0 but 3rd terminal is 1 ??

Great material. I've been working in Automatic VLSI testing since 1980. Lots of good information here. :) Thanks for sharing!

27:08 w value should be 3 because minimum weight is 3 why it's 2??

In normal mode, the input signal is an absolute means designer give standard combination of inputs and expects the output but never assumes one of the input stuck to either 0 or 1. But this stuck part happens during manufacturing...so it can be detected in test mode only. I hope this is the correct answer

korrekt, danke

Q2 27:54 For XOR gate There is no equivalent faults , EFC is cannot be done (10),(11), 0:00 0:00 (01)/(00) these three test vectors are essential test vectors of XOR gate So, DFC also cannot be done 27:54

Stuck @ 0 and 1 faults for primary outputs 17:56 So only we choose C/0 for last question of this session Is it right answer??

Good Image of DFT, decrease Test Escape, Yield Loss%. Thanks Professor Li.

Thank you professor for a great lecture. It makes clear what the scan test is than any other articles or videos. Does anyone know the answer for the question? Why can't stuck at zero fault be testable in normal mode?

Thank you professor, very good explanation.

very nice lecture, love from India

my staff literally copied your ppt 😂

crisp and clear explanation, thank-you!

what is the answer for the question

what is the answer of the question?

Thanks sir, it is a nice video. could you please explain why SE can be routed as normal signal under LOC? thanks

Are there slides available for study purpose?