Hello All, thank you for taking a pause on my channel. My name is Vartul and I am currently working at Synopsys in VLSI domain. Being from a non-IIT/non-NIT background, this journey from being a student to an electronics engineer was full of learning and pushing myself. Soon I realized in company that how in spite of producing lakhs of electronics engineers every year, there is actually a scarcity of good electronics engineers. This leads to many vacant positions in the company waiting for their right candidates. This inspired me to tell my story, my journey, my learning to you all budding electronics students. I have started this channel NOT to teach you, NOT to motivate you, but just to introduce you all about the areas and opportunities in the electronics engineering. I invite you all to this family where we all will learn and grow together. Please subscribe and become a part of this family.
thank you very much sir! after yrs i m now comfortable with what is fermi level! thete is one doubt 20:00 the positive of vbi is at p side and negative at n side according to the diode symbol drawn. but in the semiconductor diagram with the depletion region, there if u see, positive of vbi is at n side and negative at the p side. pls clarify.
Sir aapse baat karni hai mai bhi electronics me kaam karna chahta hu 2023 pass out hu aur it je jhanjat me tha par mujhe electronics me job karni hai pls help me how to contact
Bhai main ek cse student hu mujhe semiconductor and chips company me job lena h to uske liye kya kya padhna hoga mera programming language complete hai electronic branch se kya kya padhna hoga .. company me rtl design and functional verification ye do chiz hotta hai iske liya kya kya padhna hoga thoda guide kar skte hai ...
Hi Narayan, thanks for the feedback. Could you please elaborate on what else can be added technically in this topic? I would try to add them in a separate video.
Hi Narayan, Appreciate if you could kindly provide more specifics/details/explanations than what has been delivered by Vartul. So that it helps the community understand more on MOSFETS and its derivation of drain current in linear and saturation regions. Thank you.
Let me tell you my story, I have joined one of the service based company in july 2022 as Physical Design Engineer. They given access of tool after 2 months ,then i started learn without any mentoring and guidance. After having less then 4 month access they suddenly stoped access of tool. Then in apr 2023 they called me to bangalore from my base location saying that project is there you are onboarded. The i reached there with 3 other colleagues. Then they said project is not started yet. Then after 1 months passed by saying it will start soon. Then in may month end they satrted onboarding. But ..... again here is scam they said 4 batches having 5 people in each will onboarded every week. And they decided by simply by watsapp group call😅 and askeing like subji mandi. We placed at 4th batch they given priority to their south peoples. We 4 kept silent. Then we complained this is not fair like this. Then they arranged like 4 of us puted on each group separately. (I and my one colleague in 4th batch) Then first batch is onboarded on june 2023 starting, second batch waiting and after they delayed them too.. 2nd batch onboarded on july 2023 starting. Then 3rd and 4th batches are waiting... by saying that you will onboarded in next week for sure. July 2023 comes to ending ,until this PROJECT is also reach to half. And ya main thing they not even give the access at all anything even 1st batch. 3rd onboarded on end july. Some people get limited access. Now 4th batch remained. From may month that saying next week next week. Now August 2023 comes i come to know project is going to end 🙃. I reached them and asked "are we going to onboard or not now?!" One of the person said "now we can't do anything client has freezed now ( and relation with client is also one of the old with them)". I also asked that is there any project in pipeline for us then said not projects we see in 3 months too, then i said " if we are not going to do project please give permission to return base location " then given permission i and one of my colleague return 31st august. Now next day they arranged meeting said "you both puted on notice period". they could also arrange or say us on face to face while we are there. Why they haven't told before ,i don't know!? Given option like 6 month with half salary. I choosen 3 months at that time. One thing, there is appraisal period also come while we are there, said no fund avilable 😂, and hirning most seniors after that. And i also didn't understand why they layied of juniors 6-7. What strategy is that. Just they ruined my early carrier. 😢 Now i am not able to find any opportunity. I tried i failed , due to they expecting live project work. I doesn't have. I am now loosing technicality amd hands on knowledge. Most of hiring i seen is for 2+ 3+ poeple i have 1.4 year technically. But limited knowledge withoutany live project experience. Now more then 8 months gap in my employment 😑
Sir last kuch galat ho gya , x axis pe vds hi rhega ,y axis id rahega .. since we r seeing point where id becomes zero at which value of vds ..that is why id ko zero kia jissey at vds = -1/lambda aya . And sir tapering of region q ho rha hai charge deplete ku ho rhe usko ek video me explain krdo
Thanks Sanjeev for pointing this out. In the last curve, Id should be Yaxis and Vds should be Xaxis. For the charge deplition, I have already made a video on PN junction in reverse bias. Watch that video
@@sanjeevyadav-lw4ky Channel tapering is due to charge depletion. As Vds increases, reverse bias increases, charge depletion increases, channel length reduces
Sir , Please tell us how can we be a quality of ECE Engineer, How to get internship , you know many of us from Tr-3 colleges... Please respond us it will be helpful for all of us...
Actually both. Each abstraction level needs a separate engineer. You can watch my Job Series Playlist to know more about various opportunities in electronics design including VLSI domain
Masters in electronic design technology (analog n digital ic, micro n nano electronics, photonics, vlsi) of masters in embedded systems? Which os better?
Masters in electronic design technology (analog n digital ic, micro n nano electronics, photonics, vlsi) of masters in embedded systems? Which os better?
Hello bhaiya, Can you make a video detailing about "Memory design Engineer ", "testing and packaging" and "fabrication" section of the semiconductor market ? Want to know the various roles out there in the market in this field (especially the fabrication section in detail ) and the required degrees and resources to reach there. Expecting a video soon . 😇
