Hi there! New to this Channel ? If so, here's what you need to know -- I like to create video's on Analog and Digital Electronic Circuits, its my passion. Also I use this channel also to explore new concepts and reinvent new techniques to deliver knowledge
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Greetings. but when the term for channel modulation (1+ λVDS) is also present in the Id formula for the transistor in saturation, how do we behave later in the equation? I also need to know the VDS value at that point, it's not enough for me to just fix the ID current to polarize the MOS... how do we behave, thank you very much!!
Couldn't just 6 TGs be used for 4:1 MUX - (2 + 2) TGs for selecting I₀/I₁ and I₂/I₃ based on S₀ and 2 TGs to select one of the outputs from the previous selection based on S₁
Apart from the money from the RU-vid and etc etc god will bless you abundantly..... because whole analog vlsi lectures are at one place.....the way you kept all the data is very impressive.....
Hi sir since this circuit is exactly the same as a practical integrator how do we differentiate this circuit in application between intigration or filtering? Are there any critical points or cut off frequencies where the circuit does not behave as an integrator anymore or vice versa? Thankyou
Hi sir, thanks for the great explanation. I had one doubt: Even when Output is at +vsat, which means point C will be at +Bvsat and since Kathode of D2 is pulled down to ground through R4, wont D2 alos be forward biased during that time as well?
Hi Sir thanks for the great explanation! I had one question: Why wont there be any effect due to positive feedback since non inverting terminal is also connected to Output of op-Amp via resistor R
Thank you for information but I would like to know: Why the SCR activation pulse width is not the same time the SCR is passing current ? Please explain this
we generally see that the volatge across capacitor will become 0 as soon as the trigger goes low,nut in the simulation it doesn't seem like it is effected .can you explain why sir
