Welcome to the youtube channel of the solid-state circuit design lab, IIT Kanpur! We are a part of the Microelectronics & VLSI group (MVLSI group) in the Department of Electrical Engineering at IIT Kanpur.
In this channel we will share our class-room lectures of multiple courses pertaining to analog and digital circuits, and some conference talks that the group members typically deliver in conferences all across the globe.
Greetings Professor. At 36:37 the pMOS has little to no Vsd. Vy (Drain of pMOS) is at VDD (almost) and Source of pMOS is also at VDD, that should yield a Vsd ≈ 0 V. Shouldn't that make the current ≈ 0? Even with the Vsg ≈ VDD, Source and Drain are almost shorted and no current should flow. But, how are you saying that it will conduct current? Can you clarify this?
there is a switching pmos whose gate controls the Vx or Vy voltage to be Vdd or not when switch is on Vx and Vy will be at VDD so no current flows it is the reset period in the comparison period the switch is off so there is no fixed voltages at Vx and Vy at that time current flows and positive feedback regeneration happens
Thank you for your video. When you show that time interleaving images gets canceled (let's say for the case of 2XTI), you use fs/2 as the frequency to calculate the phase for the second sub-ADC, 2pi X f X Ts = 2pi X fs/2 X 1/fs = pi and hence e^jpi = -1. But when the tone is at fs/2+fin why you don't use fs/2+fin?
These are some of the highest quality lectures which explain complicated topics in a simple way. Thanks to IIT Kanpur SSCD group for making these lectures publically available.
