How can F=HGb be independent of gate sizing if B is dependent on the ratio of the path capacitance to offpath capacitance. If we resize the gates, the branching effort will change?
How can we determine branching effort bi without knowing the actual size of the logical gates as they are dependent on the capacitances of the gates driven by the driver gate?
at the start, why you say that in the pmos net we've 2C? I understand that in the N net you need that 3C because of R/3 and you have 3 so you obtain R. But shouldn't you have to put 1C , because the worst scenario is R in the pmos net?
For the PMOS to have same strength as NMOS, its width must be twice. That's why 2. You may look all values as multiple of some width W. Say 3W would be the width for each NMOS and 2W for PMOS.
You may or may not be checking your comments anymore, but I just want to say thank you for making your lecture material available online! I received my masters degree in Material Science at UCSD, and I am now working as product marketing in precursor business for semiconductor. I often find myself talking to OEMs and device makers, with little to no knowledge in ICs. Your lectures are super helpful to have meaningful conversation with my customers!
30:30 I think it should be Jc1 = m*Jc2, since current is same & Q2 is m times larger, it's current/area must be m times smaller. I know the numbers were just mistakenly reversed.
Very well explained Sir. Thank you ! I am curious about one aspect in @43.13 ; wont the three electrodes form a kind of potential divider in the electrolyte? Hence wont the physical distance between the three electrodes affect the current flowing into the counter electrode ?
you saved my life with this tutorial , i had a school project and i had a huge problem which is how can i get a heart beat signal to use it in python later . I coumdn't find any useful info in the net . When i found this vid , everything got fixed ... thank you
You're not just a lecturer but a teacher and a good one. spending 40mins watching and critically noting down points is worth it and by far more than the 72 hours i spent on the chapter in class.. thank you so much.
"CMOS VLSI Design: A Circuits and Systems Perspective" by Neil H.E. Weste and David Harris is a highly recommended book for VLSI CMOS design. It covers the basics of digital integrated circuit design using the CMOS technology and provides a comprehensive overview of the principles and techniques of modern VLSI design. The book covers a broad range of topics, from basic transistor operation and logic gates to complex digital systems and manufacturing issues. The book also includes numerous examples, exercises, and case studies to reinforce the concepts discussed. It is widely used as a textbook in undergraduate and graduate courses on VLSI design and has been praised for its clarity, depth, and practicality.
At 9:10 you said that the worst case scenario would be to calculate 1 one transistor turns on (the other 2 are switched off ) but in pull-down network you calculated all of them switched ON. This is a mistake therefore making the rest solution false.
If you ever had a chance to get interviewed by Apple related IC design position, you would be regret for not coming here earlier, thanks for the lecture, prof!!!
Prof, please allow me to add some memo here to explain why there is 2 on PUN and 3 on PDN: To equal PUN and PDN drive strength, assume the both network resistance: PUN-R = PDN-R = R, and we know for each transistor in PUN, it is generalized with 2R/K and for PDN, it is R/K So, for PUN-R: 1* (2R/K) = R, K = 2 For PDN-R: 3* (R/K) = R, K= 3 That is why PUN has 2C on both drain and source of each transistor and PDN has 3C on each…
At 40:00, I can't see any advantage in CMRR at all, compared to using the same gain of 80 dB (10,000) with the single op amp difference amplifier design mentioned earlier. The improved CMRR just comes from using a gain of 10,000 instead of 100. It appears to be nothing to do with using a fully-differential-mode amplifier before the difference amplifier. The only benefit seems to be high input impedance (which is definitely a great feature) but that could be achieved with buffer amps. In fact, the three op amp design reduces the allowable Vcm common-mode voltage compared to the single op amp design (otherwise the output of the input amps will saturate due to gain in the first stage). The only advantage I can find is the ability to set/adjust the gain with a single resistor. Or am I missing something here? Thanks!
I agree with you about the CMRR part. But I think the reason why we usually not use a gain of 10,000 instead of 100 may be that such a larger feedback resistor is hard to implement on chip and the matching will get worse too.
@@chaowang772 I take your point about large resistors, but, for example, a gain of 10,000 can be achieved with 100k and 10k. I've seen amplifier and other chips with >100k resistors - far easier than 10M for example. Also, my understanding that matching resistors is easier on chip - for example by laser trimming - and they remain at a more balanced temperature, etc. Why would the matching get worse (given that we care about relative errors not absolute errors)?
It's because 1% is a high tolerance for this application. You would typically use matched resistor networks with relative tolerance below 0.025%, which bumps CMRR a few orders of magnitude.
@@skylerpretto1221 he used curled d bcoz 'p' is another variable although F is constant, we only want to differentiate w.r.t N only keeping p as constant.
At 02:45, this comment is basically back-to-front. American doctors almost always say EKG whereas I believe almost all of Europe says ECG apart from when speaking in German (and the probably most of the rest of the world). Certainly in the UK it's only ever called ECG.
I am teaching microelectronics for the first time this semester. I've been rewriting the labs, seeking to make them more engaging. Early on I identified ECG measurement as something that would have broad appeal. Needless to say I've had limited success getting my basic circuit to work. Thanks for sharing this lecture series; it will help me take a lot of the guess work out of my design process. Your lecture is well organized has quality content and thoughtfully presented; your students are lucky to have you.
