Will changing the Switching Frequency, i.e Timer Value affect how long the counter will count for. I am having trouble where the counter will count to 255, but still be at 188 and switch duty cycles which causes a high. So it does not finish counting to 255 and resetting.
I think that loops in verilog aren't synthesizable But the generic one bit mux violates my expectations So, what it the state for my design code from synthesbility if I resorted to loops in
according to texas instruments documentation at the below link page 24/51 , I think the waveform of operation modes are exchanged www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf?ts=1719455710938
Thanks for such an awesome explanation. I have a question if you can answer. if there is a timing violation and the output goes to the metastable state but do we get the correct output once it comes out of the metastable state or the output can go to either of the logic high or logic low as can be seen the waveform at 4:57?
Sir, the way you teach is way beyond wht we get to learn in academics, ur videos have essence of partical implementation, which change the way we infer the logic and its implementation in verilog, Thanks for all the resourses that you provided, I wanted to admire your work, thanks for the help.
Changing D @ the onset of pos edge and it got reflected in Q ; doesn't it violate the hold time condition ? The previous value of D should be reflected @ Q ?
Sorry, but I think there is a mistake in the B part. It’s asking about the left side, not the right one, so the answer should be V(left) = -212.77 mV Correct me if I’m wrong please
10:55 The thing I have trouble understanding is how it could have been a combinational circuit even with blocking assignments. Don't the blocking assignments imply registers, and doesn't that also make it sequential? In my mind always_comb should work just like continuous assignments, so I have trouble wrapping my mind around why so many always block constructs (like switches) demand blocking assignments
Do we have to write the synchronous part in combinational always block? Wouldn't it work like this: always @(negedge clk,negedge reset_n) begin if(!reset_n) Q_reg <= 1'b0; if(!clear_n) Q_reg <= 1'b0; else Q_reg <= Q_next; end
Yes, that is equivalent, because if "not ~reset_n", that means that the first "always" block was triggered by a negative edge of "clk", thus you're only checking "clear_n" on a clock edge and so it is synchronous. (I also elaborated the design using your suggestion and it results in the same schematic).
Hi brother, I got a Friend that needs the whole schematic for the M9. We are in Brazil and it's difficult to find it here. He needs to check some parts to be replaced on one of that. Do you know where on internet can I find it? And if you have it, would you share it?
