I think I would go for reading/writing to SD card before real spinny disk. much simpler interface but still has a real filesystem. If you really want to pursue genuine spinny disk , it will be easier after the SD implementation as you will already have the filesystem drivers built in software. I'm happy you brought up mass storage as I had not planned that far ahead in my (still vapor) build. As far as vias go, I have seen boards with at least a dozen layer changes on some signals. Not necessarily the cleanest board, but at less than 10MHz, not at all critical. When you get up to Ghz, controlled length signals becomes a requirement to get the signals all arriving at the same time. Plus controlled impedances. You may have seen weird squiqqly traces on newer pc motherboards. that is the controlled length part. A lot of consumer products use single sided boards and lots of jumpers to get signals around the board. I wouldn't stress on the vias. If you are really worried, apply solder to them, sometimes the through plating isn't perfect and filling them with solder will help with reliability. Wave soldered boards filled the vias as part of the soldering process.
@grumpyoldman5368 -- I believe that CompactFlash cards actually have the IDE protocol built into them and you can chose between that and its native hardware interface. I am/was considering using that. But if the IDE interface is built into CF, why not use an IDE drive? Moreover, if IDE drives are now referred to as Parallel ATA (PATA), why not look at Serial ATA (SATA) since they use the same protocol over fewer wires? The short answer would be because I might not be able to achieve the speeds required. But I really do want to get some form of electro-mechanical device into the build. Or at least attempt it. I have plans for a tape and I actually have a good plan for its implementation. So, let's see where this all leads. Thanks for the information on the vias. What I take away from your comments is that while it may be necessary, it is not really best practice if I am ever going to do anything at a higher speed. It is better to keep the vias to a minimum whenever possible.
@@eryjus4594 You are correct that CF cards have an IDE interface. I thought all of the IDE modes required DMA at relatively fast speeds, but PIO mode 0 does not, so it should be doable. Did you have plans for DMA support? Not sure SATA is very hacker friendly. What kind of tape drive were you thinking? I spent 10 years repairing drives of all types in the 90's. What interface? Pertec, QIC-02, QIC-36 or something further up the food chain like SCSI. There were a few IDE interface drives, it think that was QIC-157 for quarter inch drives. 9-track was usually Pertec or SCSI. The old DEC TK-50 had a serial interface. If it were me I would probably do a Cipher or Kennedy 9-track for that old-school reel-to-reel look. The overland data drives were awful. Regarding PCB layout, generally shorter total track is better than not. If a few vias will get you a shorter track, you are better off than routing around a problem just to stay on the same layer and avoid the vias. BTW, congrats on 100 videos!
I would want to add to the conversation that it's not really the switching frequency what causes trouble to signal paths (for example unacceptable skews on clock signals, or unacceptable delays on data paths due to signal rebounds or degradation of signal integrity ), but the rate of change of such signals. A particular PCB may work just fine with HC family chips, yet fail with faster LVC or even AC chips, even if the clock frequency is set to the same relatively low value.
@RelayComputer -- I think this confirms my suspicion that the rise time and not the frequency is the major concern. Which I mention in the video. That said, what I did not account for at all was that the HC logic might just have a fast enough rise time to give me trouble -- even at 1MHz. It might be an expensive mistake, but that's how we learn. I willing to give it a go!
@@eryjus4594 I am not experienced enough to categorically say this, but I believe the HC family is very robust regarding signal integrity compared with anything else. I think it's because output pins have an impedance near 50 Ohm, yet rising/falling edge times are not extremely fast. This means that if the PCB traces are designed with some sort of impedance control in mind, even if it is not exactly 50 Ohm, there's little else we need to do for reliable, clean, signal transmissions. This may explain that projects with very long traces such as the one from James Sharman (@weirdboyjim) just work with very little attention to these possible issues
I think you have trace width design not properly understood. With cmos logic like the HC family you are using, there's not such a thing as voltage drop. Input impedance of such ics is extremely high, thus there's virtually zero current travelling along the lines, so no voltage drop whatsoever. What you need to look instead is proper characteristic impedance matching, and sometimes this implies adding termination resistors to the transition lines and narrow tracks. The HC family ics have output impedance and raising rates that generally allow for no explicit additional resistors, but characteristic impedances must still be honoured to get a perfect transmission on relatively long lines. The Kicad PCB calculator tool has a section that helps with track design to achieve proper impedance matching. Ideally, you should aim for 50 ohms transmission lines with HC family ics in order to avoid terminator resistors, but unfortunately this is hard to achieve with 2 layer PCBs. On the other hand you will get improved reliability with 4 layer PCBs, although it's difficult to tell if that's really necessary in your particular build. I think that traces less than 200mm long should be fine if you keep them sufficiently apart from each other and avoid branches
@RelayComputer -- You mean your video: ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-S3HCY2-y6p8.html I watched it and I have to admit I found it little hard to follow. The failure is mine. I can speak some Spanish (well, more like Mexican-Spanish than Spanish-Spanish) and I find myself watching the video more than reading the subtitles. As a result I did not follow it completely. I will have to take another much harder look at that video. Thank you as always for your guidance.
@@eryjus4594 Yes, that video is my attempt to explain this kind of issue. I'm sorry the video is not in English. I'm fluent in Spanish but it is not my first language, so that may explain some deviations from neutral accent... it's certainly more near Castilian-Spanish than Mexican-Spanish though. Unfortunately, my spoken English is almost inexistent because I only learned the written form by reading books and interacting with English online speakers (you won't believe how problematic is for non-natives that the English language is not phonetic). My first language is a minority one, so I chose Spanish instead as my second best option based on global number of speakers. Anyway, going back to the subject, what is shown on that video is just one of the possible problems that may arise when designing PCBs. There are others such as signal cross-talk, power distribution network, ground return paths, clock signals skew, and probably more. I learned a lot from the Robert Feranec channel (@RobertFeranec), particularly after watching a couple of interviews he conducted with Eric Bogatin, which is an extraordinary teacher and adviser about all subjects relating signal integrity
