4. 3-Bit Asynchronous Down Counter in Hindi | Tech Gurukul by Dinesh Arya 

heisenberg wants to thank you for all these videos in digital logic. Heisenberg is currently pursuing engineering in Nepal

itna a66a aur easy tarika se ap sikhate ho....matlab seriously it's awesome ....ab to ECE 2nd sem ki sabse favorites subject ban gya hai iye.....kash baki sare subject me v aysa koyi coaching mil jata.......whatever sir, huge respect for you and thanks for this awesome tutorial ......

Best teacher of digital electronic

Thank u very much Sir for your lots of efforts..... These lectures are easily understandable..... 🙏🏻🙏🏻🙏🏻🙏🏻🙏🏻

Sir, aap bhut achcha pdhate ho. Aap ne DLD ko ek dm easy bna diya hai. Thankyou sir

Nice explanation sir😊😊😊😊

Sir your teaching techniques is great . ❤

Very well explain sir thanku it's very use ful lecture continue karte rahe sir

A lot of thanks from me , sir .......very good video with nice explanation..😊😊🙂🙂

both teaching and content are awesome 🙏💯💯

Really good explanation sir... U are best sir

Lajawab sir

Cristal clear lecture... thank you so much sir

Thank you sir

Thanks a lot 😊

Very good sir g

Super explanation sir...

Thank you sir 😊

Why use a positive edge clock for down counter and negative edge trigger clock for up counters?????

Thanx sir. You explain everything very well.

Thanku sir

Good explanation

Hello Sir, Aap ekbar positive edge se ek UP Counter ka vedio korenge to bohut Achcha hota sir.... Please it's my request sir

🙏🙏great lecture sir

Great 😊

Sir, like in the Up counter where after Up counting from 0 to 7 the counter returns to 0 , after Down counting is over from 7 to 0, the counter state will return to 7?

Thank you ! Sir....

Lovely sir❤️

Nice video sir ji ❤️❤️

Thanks for your help and support.

Thankyou Sir

GREAT AND SUPERB SIR. BUT COULD HAVE BEEN BETTER IF EXAMPLES ARE SIDEBY DONE.

Hello, I'm unable to understand how Q0 first positive edge triggered FF1 and Q1 positive edge triggered FF2 simultaneously. To make down counter we have to consider notQn instead of taking Qn as output. May be I'm not able to get this and nobody pointed out this in comment section.

Great 👍

Thanks 😊 sir

super explanation sir .thanks u

Nice video sir

Sir -ve edge and -ve Q to Down Counter hoga na ???

Exam me flip flops ya other pencil se banaunga kia

Sir @14.20 agar dono sign "-" ve ho to down counting hogi?

nice

sir what type of counter is formed when negative edge is used with negative output

sir yeh jo counter hai up mode aur down mode main to kya up mode main main dono m se koi bhe flip flop bna sakta hu.postivi clocke aur negative clock same as negative m bhe

To use in toggle mod why we kept " j " and" k " at logic-1 ,as we can kept it at logic-0 to use as a toggle mod. Please reply 🎤

Sir g your digital electronics are available?

Sir 4 bit counter ya down counter ko explain kr do please

hi, sir, what about -Ve & -Ve and -ve & +ve

Sir ager hum -,-Q0& edge tringing ka lenge to Down counter bnega na

❤️❤️❤️

👌👌👌👌👌

Sir idhar -ve edge de saktay hai kya

sir aapne diffnation, up or down counter mai same note kiye hue hai 🙏

Asynchronous down flip flop main JK dono terminal ko toggling mode main karne kain leye short Kia hai Fir unko ek logic 1 line se short kar deya. Par Synchrous up wale flip flop main JK terminal ko short to kia but unhe logic line se short q nahe Kia. Book main to up, down dono flip flop ko Kara hai short. Iska Koi reasion.

Sir exam me..logic gates pencil se ya pen se banunga Ki

Sir positive edge triggered kyu liya

Sir kya AP notes de sakte ho

-ve clock hogi naa

Thanks sir