Lattice should lean deep into open source and allow hobbyists to program the bytestream. We have OpenLane, YoSys and all the fun stuff. Lattice could be the number one supplier of FPGAs for hobbyists. Look at the MISTer fpga retro stuff Neither Xilinx nor Altera are doing it.
A software stack without composabillity is just another word for monolith. And the larger the monolith becomes the harder it is for open source implementations to replace the pieces. I'm not sure where Lattice stands in this, but the competition is weak. I remember the ICE platform had a healthy open source community, hopefully Lattice sees the value in that and documents the bytestream and other communications between software components. I don't expect them to open source their secret sauce but going ahead and documenting what's already going to be reverse engineered would save everyone a lot of time.
Agreed. Tooling and software is the worst part of FPGAs design. Horrible licensing, outdated interfaces, poor scripting, if any. Open source community created better solutions despite needing to reverse engineer some bitstream formats. Lattice actually does better than others in this area, and I hope they improve it even further. There is nothing new in midrange from other market players for a decade, and prices are outrageous. I also do hope they provide some alternative to Zynq, hopefully with RISC-V based cores.
@@movax20h I personally find writing the languages the worst part of FPGA design. There just aren't great libraries with easy object-oriented programming. For example when implementing i2c on a device, you would only want to define what happens at each byte that is send/transmitted. I don't want to be bothered with implementing the rest of the protocol.
Good to see other FPGA companies are taking up the slack left by acquisitions. Kinda sad that Intel hasn't really done much with the altera FPGA tech they bought. Kinda feels like it died inside Intel. Hope AMD puts more resources towards xilinx new AI focused FPGA platform. I'm hoping AMD moves towards tenstorrent graph computing model for future Xilinx product.
Arguably Intel has done plenty with Altera. Agilex released a few years ago. Their DirectRF chips are releasing soon that will compete with RFSoC offered by Xilinx but will have even higher bandwidth. What they haven't really done is take much market share from Xilinx because customers are very vendor locked in.
@@Darkknight512 is anyone aware of them pushing FPGA for ML? I know that Microsoft help convince Intel on FPGA when they started their BrainWave project. I haven't kept up, too many things changing too quickly.
@woolfel Plenty of stuff going on in that area. Look up OneAPI, Intel's offer for heterogeneous hardware development. Also, they produce plenty of IP for AI specific applications that you can find in the IP Marketplace
@@liam_weight sadly OpenCL was dumped by Apple and NVidia pays lip service. The other AI stuff I've seen from Intel hasn't competed well against NVidia. When Microsoft showed off brainwave, I was hoping Intel would pay microsoft for a copy of the code and incorporate it into a AI software stack. Sadly that didn't happen.
@@woolfel Try searching "Intel FPGA AI Suite" and messing around with that. I've done hardware acceleration for AI in the past using Intel FPGAs and have had great success, beating an A100 (at $35k part) using Resnet-50 in FPS with an Agilex M (around $7k for a DevKit, a 5th the price). Honestly the fact you're saying Intel have not done anything in the AI space makes me think you just haven't looked. Their new chips have a RISC-V processor on-chip, so you can have a full SoC solution solution if you wanted. I built out a direct data ingest coming from a camera into an AI pipeline, for defect spotting on an assembly line, and it was cheaper, easier, and more available than anything on offer from NVIDIA at the moment. If you've got a Terrasic DE10 Agilex devkit available, I guarantee in just a day working with their AI suite you would change your tune.
Was reading up on the PolarFire FPGAs somewhat recently... looks like Lattice is redefining the "mid-range FPGA" segment because, on paper, this appears to be a completely different class of FPGA.
FPGA potentially future-proofs some aspects of computer designs. For example a thin-client with 1080p display really should be able to keep doing its job for decades, so long as it can communicate efficiently and maintain/update its peripherals. If its USB were implemented by FPGA it could talk future dialects. If its ethernet/WiFi/mobile data were implemented by FPGA, it could talk anything that fit the spectrum, bandwidth and modulation capabilities of the modem hardware and media. An early 3GPP system could have been updated to 5G-NR spec. The problem with adoption for those purposes is that most manufacturers see future-proofing as a manufacturing anti-pattern. Especially in tech, which seems ironic, but rapid iteration has been part of rapid innovation and without selling new tech to everyone every 2-5 years the economics would fall apart. But it's bad for the prosperity of the world. If things were made to last and there was an emphasis on re-use / refurbishment / post-premium lifecycle, then instead of tech landfill, there'd be tech trickledown, and we'd start getting the same long-term societal benefits from tech manufacturing that we have been from well-built shelters, which are what created cities and elevated us from living in trees and caves and huts. But instead we have a de-facto standard of cost-optimisation as an excuse for planned obsolescence. Some day I hope we have a tax on how disposable a product is within its class, to encourage the long-term wealth of society.
Audio is better, but ~3 dB lower than the ~6 dB of standard output levels. Great set for recording. If you're shooting a flat video profile, you're lacking brightness and contrast and what should be adjust for appropriate exposure is dependent upon your NLE. If you're using the standard straight-out-of-the-camera profile, you're underexposing by about 1 stop; increase lighting levels, open your aperture, or increase ISO by 1 stop.
I would have liked to see a RISC-V hard-core, yeah you can probably afford to fit a soft-core in, but I feel like that is a bit of a missed opportunity
Great video. Now we need another one, with a more detailed explanation how these kinds of chips are essential for modern household appliances and cars.
So is Lattice targeting the Retro Enthusiasts and the multitude of Retro products based on FPGas? Such as RetroTINK 5X or the MiSTer Project, Clone Consoles based on FPGAs
I'm curious about what kind of AI accelerator for development / learning would suit me. Currently I'm just using a 5950X for teaching myself different neural network designs and thinking that I would love to learn the difference between a "normal" GPU accelerator like Geforce and Radeon compared to Tenstorrent and these FPGA solution. Questions come to mind are like pros vs cons for each solution in categories like price / performance, performance / power, what kind of NN designs are more suited for each solution, NN scaling, NN design flexibility (can we use a non standard "linear" NN design), learning vs inferencing, small user (like me) vs mid and large users e.t.c. In other words maybe there could be a video directed to us who wants to scale up with accelerators, maybe an FPGA solution might be for some of us? Or a mix of them for use in different stages?
Microsoft uses FPGA for software defined networks (SDN) and small ML models. Brainwave is the framework microsoft wrote to compile neural network models to run on FPGA, which means it runs at real-time versus on GPU. The catch is the model has to be small enough to fit on the FPGA boards. It's hard to know exact scaling between GPU v FPGA v ASIC, since no one has published a detailed comparison. The primary limit at runtime is how much memory do you need? Right now, that kind of dictates the hardware you deploy on. For training, you can adjust batch/mini-batch to fit in the memory you have with the usual trade-offs. Azure has a toolkit to accelerate some models, but it doesn't work with everything yet. Right now there's a half dozen kinds of models hardware accelerator supports, but hopefully they support models in the future.
It would be great if you could have a 3 axis graph of power , performance ( speed and number of logic elements ) , and price - then position the players on the graph for a midrange segment eg Efinix , Lattice etc and discuss pros and cons importantly available ip such as RISC V cores , Ethernet Mac and ability to run OS like embedded Linux
I have seen large Xilinx FPGAs in cameras, from Blackmagic design but also very specialized thermal cameras. But not sure how large of a market that is. I can now see why the white paper video idea isn't very successful, also white paper seems to have become a reference for the color grade?
These guys should consider embedding a few different Risc V ASICs on these, you know using different extensions depending on requirements (as well as number of cores etc)
Wow, am I open to some other vendor providing mid range FPGA's! Intel (formerly Altera) and AMD (formerly Xilinx) have done some quite questionable things in the past 3 years. Not being able to source many of their parts being the worst of all. I hope Lattice can step up to the plate and provide parts that'll have tools that are supported beyond the short term horizons that Altera and Intel have decided to tread. Trust me, makers and hobbyists what will be the future industrial consumers of your parts will appreciate that. Oh, and I hope you'll not follow the anti-pattern of making your proprietary development tools a profit center.
The problem isn’t the hardware; it’s the IP, documentation, community, and tools. This is where Xilinx is crushing everyone else. Vitis and Vivado are much more usable and less buggy than Quartus or Lattice’s suites. That’s not really praise for Xilinx, just highlighting how bad FPGA tools are in general. Well, also there is no hard ARM core. I don’t see using this over Zynq 7000 or Zynq Ultrascale+. Almost everyone is moving to the parts with SoC.
I'm not sure why Agilex 5 wasn't mentioned in this video at all. It's Intel's new midrange chip (which competes directly with Avant) that was announced early this year. As far as I can see looking at the announced specs, it outcompetes Lattice in almost every area except for die size.
Intel did a really bad job at announcing them. I'm looking through my inbox, no mention of a briefing on Agilex 5, no contact with the old PSG in a long, long while, even though Intel pays me as an analyst to keep me up to date. In the past when Intel have announced Agilex FPGAs, they're typically a year+ out from actually coming to market. I've looked around at the usual places, and it looks like Intel didn't tell anyone. I'll bring it up in my next call with them. Edit: Looking through the brief now. Aren't they simply cut-down big Agilexes? Tbh, now I've put out this video, I wouldn't be surprised if Intel pokes me a bit more on their Agilex strategy.
@TechTechPotato Agreed. The press and analysts should be way more aware of it than they are currently. Not sure what's up with the marketing. Intel has split their road map into all Agilex; 9, 7, 5, and a yet-be-be-announced 3 (it's in the marketing mix, but no specs have been released as of yet). It was all officially launched at FPGA Day in November. Looking at the whitepaper they released, the Agilex 5 specifically seems to have a distinctly different Transceiver/IO complex, different HPS, DSP block, and a TSN controller, as well as some other things; it doesn't seem to be just another Agilex 7 SKU. No idea about the pricing, but it very much looks aimed at the mid-market segment.
On server heuristic anti spam on every server. Hopefully sharing resources. Sounds insane but not for long. What's more insane is that they aren't at the cutting edge of ML more than they are. Everyone calls it AI but it needs a human approach to make it actually human to deal with.
Why is Intel Terasic Cyclone V the only possible product on earth that's affordable and available for hobbyists? The same kind of people who buy Raspberry Pi buy the Intel Terasic DE10-Nano. For example the MiSTer FPGA retro gaming community is stuck with Intel DE10-Nano with 110K LEs and there's definitely no competitor and no cost effective alternative anywhere in sight coming anytime soon and that's not going to change as far as everyone says. But DE10-Nano does not have enough LEs to emulate a 486 DX2/66 which is something people want for DOS gaming for example. Does anyone have an idea about when or how there could finally be something that's more capable than DE10-Nano available for the hobbyist community?
Isn't DOSbox enough for that? I mean, I get that FPGA is the way for many arcade and console emulation but for old x86 PC games it seems a bit extreme.
@@zyxyuv1650People who are convinced the only possible hobby project is MiSTer, and don't want to consider the effort of porting it anyhow, mostly. In contrast, Mega65 runs some MiSTer cores on a Xilinx FPGA. That 486 core they don't like the performance of is clocked at 90MHz by default; I don't know where the bottle neck is. Most likely the speed is design architecture limited, not FPGA size. These retro projects are often not written very hardware oriented.
I wonder how/if these could be used to make Crypto Mining Hardware for more hobbyist level miners like myself? I really really would love to get my hands on a Xilinx C1100 but they're unobtainium for someone like me that doesn't have 20k for one board lol. I've found the actual FPGA chips for relatively affordable pricing directly from China but that's useless without the associated accelerator PCB design around it😞
WTH did I just watch? 🤣 I know very little about FPGA's, so fair warning to people who will watch it without prep - this is slightly different than your usual gaming/server CPU's. :D
Not that it really matters... But what studio is that? Is it another RU-vidr's set up? I assume so based off the silver play button but I'm not sure who's it is.
I Love Hate Lattice FPGAs. Great products. I use their FPGA in many designs. But now out of stock... with 60 weeks lead time :/ Unfortunately there not many alternatives from other companies.
Focusing on supporting int8 is a mistake, studies clearly have been showing that bf16 (fp16 for non-supporting hw) as the best result for quantization. We know int8 is just not accurate enough for most scenarios, you're better off just spending time pruning and other methods at that point.
Are you talking training or inference here? Inference for a number of work flows has already been suitable down to INT4, and there's a lot of demand for INT8.
@@TechTechPotato I think for the most part, we're not going to see training on these devices. So I'll primarily be focusing on inference. Looking specifically at numbers it seems like you still take a large hit for some models with 95% accuracy still being the top end for int8 quantization. I'd rather handle some custom formats (such as MSFP), which are exceedingly better for memory/MAC area with higher accuracy. Although I guess it really depends on the application.
Your movement is way to unnatural, whatever seminar you went to or video you watched on body framing and movement while giving a presentation just forget it, chill be yourself.
This is what I'm like when I'm presenting solo. You'll notice I move my hands in cadence with how I'm speaking. No seminars or formal video here, though I've learned since that it's a good technique for introverts not used to doing formal presentations.
I don't think Ian is too concerned with however he moves. There are more important things in life. 😂 UPD The funny thing is this comment is the most popular because Ian responded to it.
@@TechTechPotato To me it feels weird the eyesight being fixated most of the time at the camera. While I don't have a personal experience, I would imagine that talking like to a public instead is a better presentation and not so distracting. Thank you for your in-depth tech channel btw, more appreciated than the "sensational" approach others follow.
