Fantastic,thank you, I am testing this circuit on my laboratory ups with 8 batteries and it works great! I used to get unbalanced damaged batteries often in the ups system.
Dear Professor, Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype. Hope you will soon upload a video... Best Regards
Thank you for sharing your fascinating idea. The given circuit definitly reduces the balancing time compared to the conventional switching capacitor method. Which is a very good performance. Here is a question for the frequency part. I think that a switching capacitor method adopts a fixed duty ratio (0.5 not considering the dead time) with low frequency and usually lean on the cell performance for automatic balacning. However, if the switching frequency is set to be high to reduce the balancing time, won't be the loss caused by the passive components (Cap & Resistor) and Active components will out surpass the advantage? thank you.
Was this simulated in LTspice or another program? Also to represent the cells what did you use? I tried with a large capacitor with a reasonable ESR but i am not sure how large should i set them, to be ? 1F 100F ? more less?
Hi Sir could you please make a video on 3 phase active PFC circuit using LTspice... mainly for less than 1KW design what sort of PFC topologies would be preferred ?
Thank you for the video, it is informative and straightforward, as always. The idea is elegant and implementation seems simple. I have one doubt regarding the approach to recognition of the stack of cells being fully balanced. Let's assume we have 4 cells: the upper one is the cell 1, then cell 2, cell 3 and cell 4 connected to the ground. If the cell 1 and cell 4 are having the same voltage, so do cell 2 and cell 3, however cell 1 (or 4) and cell 2 (or 3) voltages differ, then by comparing voltage of cells: 1+2+3 with cells 2+3+4 we obtain the info that all stack is balanced, which is not true. Am I correct, or did I miss something? Regards!
The auxiliary path balances cells 1 and 4. It does not sense 2 and 4. But, deviation of 2 and 4 will quickly spread to 1 and 4, so (as said in the video) there is a need to wait.
So this entire array would need only one half bridge driver , if I understand well . Is there any concern with all that current spreading to all the FETs , so they turn slow. Also what would be an appropriate size for the caps? I assume they are large electrical or tantalum so like 470u or larger? When it comes to that low side sense resistor, the output from the op am was also negative so the op am needs a negative rail and that is not nice but I assume the peacks are more or less identical so I think only the high side of the peacks is enough for it to work, is that correct? Also ,tho this may be a bit out of place, is there a place where you upload these simulations?
Sorry to bother you but i tried to recreate the circuit in LTSpice but i cnt get the nMOS driver to work . I tried to use a half bridge driver and a 100k and a 7v Zenner diode like in the picture at 7:30 , in another video you demonstrate a diver that used a few more components , Is this that driver but simplified so it fits on the screen ?
Dear Professor, Great explanation, I request you to please brief a bit on the analysis of this circuit. Because I want to develop an understanding of the circuit not only just pick the circuit and develop the prototype. Hope you will soon upload a video... Best Regards
