Arm vs RISC-V? Which One Is The Most Efficient? 

2010 does indeed seem 23 years ago

Gary, there was an article that i read about a week age that Apple may be shifting away from ARM to RISC-V. What do you think that Apple will switch to RISC V or continue with ARM for the time being?

Your difference may be compiler, you would need to check the assembler out with gcc -S

Blackpill costs 20-30€ here... Sad times

If you leave out everything else and just concentrate on one thing, it's possible to find some little victory somewhere. Efficient is such a vague term. RISC-V is nice, great that some people make it and I hope they get further. But my first ARM chip was an ARM2, no intention of switching camps and I see no reason to. These ARM chips were made to be low power, yet still have some performance. They do what they have been designed to do. That is also a form of efficiency; nothing wasted on doing what they shouldn't.

For measuring relative performance, it is wrong to do a per MHz calculation. The only metric that should matter is the total time needed to run the same application on both processors. A more complicated ISA means clock speeds will be reduced (which gives better per MHz performance), but that does not mean the processor is faster

One more comment. Most processor manufacturers produce a spec called DMIPS/MHz, or millions of integer calculations per megahertz clock speed. This allows you to do a clock for clock comparison between parts.

RISC-V, ARM and others like MIPS which I have plenty of experience with are just architectures; the chips you can buy are implementations of these architectures. First thing to notice from a 30,000ft perspective is that 64-bit ARM, MIPS and RISC-V are surprisingly similar. In the past CPU architects were more adventerous. These days no more bat crazy shit like segments (x86) or register windows (SPARC, and totally batshit crazy on IA-64). MIPS is an early but well designed RISC architecture; 64-bit ARM (which fortunately is rather dissimilar to the 32-bit ARM architecture) is surprisingly similar. Which is unsurprising because one of the architects used to work for MIPS. And RISC-V was designed by the fathers of SPARC and MIPS. So are they all the same? Not quite but 64-bit ARM and RISC-V benefit significantly from hindsight. Now, once you take things to the limit things will be different. RISC-V's smaller footprint allows fitting more cores running at a higher clockrate on a die. It barely matters for the birdseed class of microcontrollers that's polluting most PCBs ;- So for most uses architecture doesn't matter - software does. That's where ARM is very well supported, MIPS is well established and RISC-V is still catching up. That said, the folks behind RISC-V is smart and have impressed me by what they have achieved and in my discussion so they're going to close that gap. Plus hgiher end implementations are going to show up. Being a truely open architecture however the RISC-V market can be as confusing as a ant pile - or open source in general ;-)

Its not about performance only!!!! The biggest thing RISCV is OPEN SOURCE processor...

I was surprised that the now somewhat venerable Black Pill did so well in these tests against the newer upstarts, especially in power consumption and power efficiency. Thanks Gary!

I appricate that Gary is right here that RISC-V is not yet *as* effecient as but I'm very impressed that RISC-V is already *almost* as efficent as ARM with for the same processes being run 1.36mWh compaired to the equivlent ARM board getting 1.31mWh and even compaired to the *much* more established Pi Pico, it's only 8% less effient (than the Pico). Obviously being almost 89% less efficient than the Blackpill isn't ideal for RISC-V but this is still early days for it compared to ARM and just with there being so many less RISC-V processors produced vs ARM, I don't think you can expect it to be beating the leaders of the pack in ARM just yet. Maybe when there are as many models of RISK-V processor as ARM processors the leader will be arm. Maybe with more time for tuning, the leader of the RISC-V pack will beat the leader of the ARM pack; even with less models out there. Encouraging stuff. Stating my bias: I want RISC-V to succeed as I think open source is the way forward and garding "intelectual property" like dragons over gold, is holding humanity back. Thanks for the interesting video Gary!

A nice explanation as always. But I'm missing the sleep current for the different boards. It would be intresting to see how they perform compared to eachother. It is more if a comparison between MCU brands than core architechture, but still! :D

Crazy to use only a single RISC-V board as representing a whole ISA. Obviously not all ARM cores or boards are created equal, and neither are all RISC-V cores or boards. Espressif doesn't even say in their datasheet what RISC-V core it uses. Crazy also not to include Sipeed Longan Nano ($4.80, 108 MHz, been around for three years), some Bouffalo lab BL602 board (similar price to ESP32s, we know it uses a SiFive core) or even extend the price limit a fraction to include a K210 board (dual core 400 MHz 64 bit) such as Maix Bit. Still, it is interesting to see that from the same chip/board manufacturer the RISC-V does in fact give better performance per MHz and per Watt than what they were using before. A really interesting test would be the Longan Nano (GD32VF103 clone of an STM32 but with a RISC-V core) vs either a GD32F103 (same manufacturer STM32 clone with a real licensed ARM core) and/or a real STM32F103.

When I studied computer science Risc-V was my favorite to program. Good to see they are now doing a comeback.

It’s always strange being reminded that people think RISC-V is inherently more efficient than ARM. That’s not why people like the architecture. It’s an open standard, whereas ARM is proprietary. Anyone who can make a chip can make and innovate a RISC-V design, not the case with ARM. That being said, this was nice to see. I’m sure it has a lot of people blackpilled now.

Great work as always. Benchmarking is always a can of worms because it is as dependent on the application as it is on the processor. Do you need fast integer? Fast interrupt response? Floating point? DMA? If you used newer M3 and M4 parts they would have performed much better even in this integer-only test both with regard to processing speed and power consumption given that they’re built on *much* newer process nodes. And a recent STM32 M7 would’ve blown everything else out of the water.

Isn't the manufacturing process(how many nm) a major factor in power consumption?

I really love the black pill , actually currently I’m working on project using it (STM32F411CE), so glad to hear it did will in the benchmark, but Gray I have question Did u write the program for each board in assembly or C ? In case the answer C , then What compiler did u use for each one? I hope didn’t throw up a lot of questions 😅😅. Amazing work man, thanks a lot for this benchmark and I hope see more of them!!

You should put "power efficient" in the title.

minor but architecture can 100% be relevant for effeciency, speed, etc. Yes, a good x86 implementation can always sip power in comparison to a shit ARM implementation, but that doesn't mean implementation is all that matters. A slow algorithm on a super computer will outpace a fast algorithm on a microcontroller, but that doesn't mean picking the right algorithm doesn't matter, it just means that it's not the sole deciding factor. These architectures were invented to solve specific problems and to suggest that architecture is irrelevant is really just disengenous. No, the differences won't be direct, but the architecture influences the implementation; different architectures lend themselves better or worse to different designs, and some designs are better in some functionality than others. Intel was *_far_* ahead of AMD for a good long while, but then AMD started going batshit and putting dozens of cores on their CPUs and now at the ultra-high performance they're pretty unmatched. In single core they still lag a tiny bit IIRC, but in multicore it's real hard to beat 16, 32, 64, 128 seperate cores. Speed isn't just an RPG stat, there is a *_lot_* of nuance and 'speed' is really just the composite of how fast it can go and how easily it can go that fast. If your chip is the fastest thing in the world, but it takes 500x more work to develop for, it'll never take off. (outside of niche use cases of course) On the other hand, if your chip is 25% faster and a drop-in replacement, it'll spread like wildfire. One thing I really think RISC-V needs to work on is making sure that they go out of their way to make cross-compilation as easy as possible; that or invent a damn good emulation suite. (but only Apple has really ever pulled off performant cross-architecture support AFAIK. I hear a few projects are getting pretty good, but I've never heard of one *_really_* bridging the gap outside of Apple) A new architecture just can't demand people spend time porting their software unless they have something *_really_* good to offer, and really RISC is more of just an incremental improvement than anything.

Gonna take a while for the RISC-V manufacturers to figure out how to design really great chips with it, but there's no reason not to expect it will be roughly the same as ARM in the long run, just with an open ISA which is an absolute win on its own. Hobbyists who aren't trying to squeeze every last bit of performance and efficiency out of their projects should support RISC-V to help it along and encourage faster development. It's already outpacing ARM's development, which was already quite rapid.

I just bought my first RISC-V chip, an esp32-c3 from adafruit. Mostly bought it to learn RISC-V Assembly. Generally want to learn AVR, ARM and RISC-V Assembly.

Very interesting article. I have always thought about how RISC-V would be compared to ARM. Do you have similar comparising for enterprise chips too? comparing RISC-V with x86 (Intel/AMD) and perhaps also including ARM?

Well... There are certain extras in your core implementation that will make a difference; stuff like the different caches and the coherency mechanism, the branch predictor, cpu internal bus and the bus arbiters, there's just so many extra internals that are all abstracted away in complex logic. Some of that complex logic is just more appropriate to implement in another program, i think some of the cpu caches are governed by a whole other "management engine" that runs its own firmware to keep track of the bits in the cache....

You also need to consider the code density. The firmware binary size is usually smaller using ARM cortex compare to RISC-V or ESP32.

Useful test but not good test on the topic of CPU core efficiency for several reasons: 1. likely system bus speed differences between these (system bus interfaces to on-chip SRAM) obfuscate differences between true CPU core performance/MHz/Watt unless you downclocked all of them to lowest common denominator system bus speed, 2. differences in flash memory/prefetchers further obfucate CPU core performance unless you ran the benchmark from RAM and even then some like M3/M4 could use dual-buses 1 for data and 1 for instructions making it unfair, 3. finally at least some of these probably manufactured on different process nodes

Hi Gary, it would be really interesting to have you do a Intel Atom/E-core (Alderlake/Gracemont) architectural deep dive video, and a comparison to Arm/Risc-v.

6502 is the best.

Both are amazing and exciting alternatives to X86 💪🙏

A huge factor for efficiency is compiler quality which grows with age. The major design differences ariund efficiency is stuff like dark silicon for common tasks and SIMD engine implementation plus caches.

As I watch, I get questions, and as soon as they pop into my mind, Gary already responds to them. It's rare that a tech video is this well thought out and structured this well!

Do you have thoughts about potential of Risc-V? I was curious about any production difference, like applied node size.

I would love to see the xiao nrf52840 board or equivalent, put to the test as it is running at 64 mhz. This is the microcontroller used on a lot of smartwatches. Plus it would also be interesting to see the boards already test, retested at lower clock speeds, if that option is available. I know some esp32 can have the clock lowered. For pure power efficiency, I believe lower clock speed tends to be more power efficient for the same work done, as power usage tends to go up on an exponential scale, whereas processing power for the same processor goes up linearly. If the amps are the same at 3.3 and 5, then it is using an inefficient regulator to drop the voltage. Just curious, did you calculate the power efficiency using 3.3 or 5 volts? I am not a fan of any architect as I just use whatever is better suited to the task. Of course having one that does it all would be nice and save having to learn all the differences, but now that assembly language is rarely used, it is not like having to learn an entirely new instruction set. By the way, if anyone gets a xiao nrf52840, if they say double click the button beside the usb c, the double click speed is a bit slower double click than I was used to. Took me a lot of tries to get it right. Luckily someone mentioned doing a slow double click somewhere.

'Which one is more efficient', not most efficient. You use most if comparing more than two things. This is primary school English tuition!

Gary did you check the real clock speed of the RP2040. The maximum clock speed is 133 MHz but in the SDK it is set to 120 MHz because it is easier to get the correct clock for peripherals like the USB. Check SystemCoreClock in the SDK. Are you running the test from RAM or XIP? You probably see a difference here.

Too bad MIPS is dead

That is very slow M4, low power version? Most M4's run at 168Mhz or 180Mhz or so. Edit: And real power of the stm32 M4 is the FPU. Maybe you can do a floating-point test between esp32, risc-v and the M4.

As I see it: Arm's been around for a while. It's had an awful lot of work put into its efficiency, power, etc. over the decades. RISC-V is new, and there isn't a lot of money in perfectly optimizing it (yet). The fact that it is at all competitive now is a good sign for things to come, but it's gonna need more time, work, and support to be fully realized in this regard.

So - I've implemented an ARM and RISC-V architectures "on paper", and RISC-V is simpler in ways that pay. There's only about a dozen basic choices that even *can* be optimized out in the core ISA yielding an architecturally pure ISA. My less favorite parts: * The opcode, funct3, and funct7 not being unified in decode step. * The LU opcodes not mapping to truth table means LU operations are not simple 4BD decodes with add and mul being 2x4BD+1 decodes. AFAIK no commercially available ISA has ever achieved this, but it's been discussed widely in academic circles. ARM though has for example the Java bit which *halves* the available opcode range, and is AFAIK based on an earlier RISC platform with some commercial extensions. And sure, some of that makes it fast, but it's going to be less efficient per wire than a cleaner ISA. There's actually tons of details I don't like in it.

How do these compare with x86 chips, specifically in running programs that are designed for x86?

I actually disagree that architecture does not decide efficiency just implementation. It is not so simple! You can say that one can implement both using steam engines and valves and silicon and make a HUGE difference - but you can also come up with instruction set architectures that are "easier" to implement well on silicon or harder to implement well. The same is saying that you cannot basically tell which programming language is faster because they are just a language - a specification - not an implementation of that. Yes you can make a very dumb C compiler that makes it slower than python, but for some reason all well-made C compilers are tons faster... Why? Because the specification was made that way (or ended up that way) so that it can be more efficiently implemented both on average and on best effort! Trust me: I can come up with an instruction set architecture any day that can be only implemented garbage slowly if you don't understand what I talk about or parallels... Also would be good to have riscV SoC variants that does not have the integrated wifi... being in sleep or not existing likely makes a huge difference (if not for other, then it takes space on the die which could be utilized to have lower consumption solutions for example).

Why not transistor count instead of energy used, too many variables. Assuming transistor numbers usually correlate to cost ultimately… to show what architecture more efficient for the theoretical cost of production (if they were same fab, same node)

Unfortunately, there is no way to quantify which ISA is more efficient based on random boards from different manufacturers. There are too many variables in this equation to drive any meaningful data from these tests. One would need to custom engineer their own hardware while keeping CPU design really close to each other to be able to accurately quantify this

1:10 I did, RV32I in fact! although i had a hard drive failure so now it's abandoned...

Consider ploting these chips as a chart Power_consumption vs Time_of_execution. By doing that, we will see the best over all chip.

11:20 how can current stay the same? I have searched many and many voltage regulators. They all come with no load or quiescent current. If you don't use a voltage regulator, it must use less current. This is not complicated.

I just created a NAS with a Raspberry Pi 4B and an external USB HDD. This would be a good application to verify an SBC is useful.

I guess Gary, you really should put out a video series explaining the differences between ISAs, microarchitecture, process node etc. to the general public, as I have watched many people are disagreeing with you on various issues. I think this video series will work as prelude to ARM vs RISCC-V video BWT i also felt that I need some more help 😅😅😅😅 on this. Thank you

there is no such thing as efficient ISA, efficiency comes from physical design and layout and which nm technology chip using, ask compiler developers which one is better ISA because thats what matters. ISA is interface between chip and compiler efficiency comes from implementation not interface.

Chinese technology is becoming superior

Interesting video :) I do not think it is enough to just to power the 3.3v rail since there are other onboard electronics which also require a power (usb to serial converter) on the esp32 chip. It could have been interesting to see it compared to the datasheet :)

I think that first generation product are not going be great anyways. Just wait in the future you will get better ones as they get more experience refining the process. That is why early adopters always get screwed in the long time.

How did you ensure that wifi and bluetooth radios did not affect the power measurements?

It might be better to run multiple types of programs bc different ones may compute using different power drawing

In general, performance of risc-5 is not up to the standards of ARM. Full stop. But this battle does not stop today. ARM just announced, that they will charge their customers in future based on the device prices instead for IP. That will drive the research in the area of Risc-V up. I expect the Risc-V to become a contender in the Mobile Phone space (low end) in about 3 years and in the high end market in 6-7 years.

Isn't power consumption also a function of speed though? i wouldn't be surprised if the microcontroller's power consumption is directly proportional to the speed

Just spent three months learning the wrong instruction set. I'm a bit miffed about it

One detail that you missed is that the Pico and Pico W do not have a linear regulator; they have an on-board buck-boost switching power supply. Current consumption will not be constant; it will go up as voltage decreases.

I do wonder how much current ran through them at the same clock speed.

Hmmm ... Efficiency is largely dependent on the implementation and which extensions are used...

I am waiting for a fullsize PC with RISC-V CPU.

I think it quite surprising that a 13 year old design stands up so well. I would suspect that if the power saving features of more modern ARM processor designs were to be exploited for a micro-controller SoC, then it might do better still. However, presumably the priority has switched to producing much more powerful, low-power architectures for use in servers, laptops and the like. producing the ultimate in low power micro-controllers is probably not a priority as these things are rarely required to do heavy number crunching.

Back in uni, I still remember the active power (total power - leakage current power) is proportional to square of frequency. Can we use it to extrapolate the power usage of the pi to 160 or 240 mhz?

Its kinda wrong to average out the performance. The esp32, esp32-s2 and esp32-c3 have an adjustable clock ( 80 Mhz,160 MHz and 240 Mhz). The newer Esp32-s3 can go as low as 10 Mhz. You can set the esps to 160 Mhz to compare to each other. You can also average the time it takes for fixed set of operations etc

Were the connectors taken into account? USB C has transfer rates close to 10Gbps while micro usb is pushing over 450 Mbps. Then as far as power, USB-C handle nearly an order of magnitude power than the micro usb at 100W. Just curious.

clock speed scaling is definitely not linear enough to fix afterwards, you should down clock all of them to the same speed, if you want compare at the same speed...

Literally searched this a few days ago with all the news about RISC V Vs ARM. And there was no video. Thank you for this one.

I would have loved to see more different benchmarks hitting different areas of the MPUs, since concluding based on one very specific crypto-benchmark not even using floats seems quite off to me...

ESP32 also has an ultra low power processor.

mA/MHz or mWh/MHz is a useful metric.

Risc v only has open source as their selling point.

when china think they can produce any arm chips, they are wrong. risc-v also contain propietary american licensing things from the basic ground up to its implementations. so tough luck, china.

You are comparing what against what exactly? For ARM, there are many different versions of the ISA (instruction set architecture). v7, v8, THUMB, THUMB2 being only the major families. Let's say you take the latest and greatest of these: that would be ARMv8 with Thumb 2 instructions. For RISC-V, the situation is more clear: There is the RV32I (32 bit) and RV64I (64 bit), with I = basic/integer, and extensions M (multiply/divide), A (atomic operations), F (floating point), D (double precision). Collectively IMAFD is called G. There are compressed instructions of the I set, called C. Then there is the V extension for "vector". Also there is the H extension for "hypervisor" I think that when comparing ISA's it would be fair to compare ARMv8+THUMB2 with RV64GCVH. Now of course, somewhat decent RISC-V boards are coming available just about now, and efficient CPUs with the ARMv8+THUMB2 are now on the verge of beating Intel/AMD in laptops and servers. So it is just not fair to compare the current implementions of both instruction set families. You can compare code side: RISC-V linux executables are smaller than both x86_64 and ARMv8 for the programs I compared: ls, mv, cp, sshd, gzip. This is in contrast with what everybody claimed: C programs should be bigger when compiled to RISC-V machine language because it is RISC and the other two are CISC. Well, ARMv8 is technically RISC, I read, but compared to RISC-V the language is huge. However, code size is vanishingly small compared with data even on a Windows system. Still, RISC-V Linux has consistently about 10% to 20% smaller executables. You could also count the number of instructions executed for a certain task, say sorting an array, or compressing a file, or computing something scientific and massively parallel. Then you can compare the number of instructions used in RISC-V vector extensions against ARMv8 Thumb2 instructions. Still there is a caveat: RISC-V V extension is vector length independent. Newer chips can run the same binary more efficiently when it has a larger vector length. You can do normal performance benchmarks but then you are comparing hardware implementations, not the ISA's.

frequency scaling with power usage isn't linear, its exponential, its better to have all of them at the same clock frequency

You should have compared ESP32-C (RISC-V) series chip with STM32 WB (ARM M4) series chip. They are direct competitor in function and price. Chip from 2010's are too old. I am not impressed with ESP32-C (RISC-V). I can not find any reason to use RISC-V based controller like ESP32-C in my future project. ARM based controllers are still the way to go in performance, efficiency, and cost, not to mention ease of development.

Well is ut really fair to compare a first gem dev kit( for risc-v) to something that , I assume,a set of products that had years of optimisation ?

Good video. 13:59: Board A uses 20mA·26s = 0.52 Coulomb = 3.2448·10²¹ electrons to accomplish the task, and Board B uses 51mA·18s = 0.918 Coulomb = 5.72832·10²¹ electrons, so Board A peruses only ~57% of the electrons that Board B uses. Therefore A is more efficient.

The silicon fab processor node tech used to make the chips plays a huge role in their efficiency. It would be good to include fab node info in the comparison data.

What do you mean by efficiency? There's performance efficiency, and then there's energy efficiency.

you should also list the process node for the processor, it also really affects efficiency.

Hopefully you look into purchasing the DeepComputing/Xcalibyte ROMA RISC-V laptop (or a related RISC-V laptop or desktop) for a future video, but much more refinement will probably be necessary for it to reach it's full potential.

RU-vid Streamers n😢w want me to use ESP32 but I want to use pico or if I want more performance so I use rpi zero

Not sure if this is a valid question, but here goes. Based in these clock speeds, could one of these chips act as a processor in a micro DOS or Windows environment? Thinking kiosk that runs a corporate webpage and allows customer data entry or order entry on-site. Or tiny web book or a tablet just for web or ebook reader where its mostly text. I know that the Pi, which is more powerful and has a video decoder is slow at video and graphics. Just thinking that if not much computing power was needed, you could pair with a mid power graphics chip for running the display and decoding video streams. Then maybe you get TVs with minor computing and networking power. Or is this how they are making smart TVs?

Arm is a risc chip. Also, it stands for reduced instruction set. Actually, you will nrrd to have the same motherboard with a socket mount in order to exclude other factors in the testing, but even then the fastest chip was at 240 mhz y won't se where those can make a use maybe in remote controls, elsewhere those are to slow, or use them I a insane cluster 999999999999x cluster but you will need a dam fast cluster management running within the firmware

But shouldn't the power (aka V*I) be more relevant than the current (I)?

3:21 22/23 years ago? R u sure Gary?😂🤣🤣🤣 Anyway Gary, well done comparison, thx!

It's never been about efficiency, was always about pcore license dependency

Fantastic succinct but thorough coverage. I can tell a lot of work went into this great video. Subscribed!

great video, thank you

But which is more efficient RISC-V or ARM in Minecraft lol. But still important point that what is used to handle the instruction sets matter way more than instruction sets themselves.

It would be interesting to know also the idle power consumption, it would give an idea of how the boards would behave when powered with a battery.

You mentioned that you encryption algorithms don't use floating point or integer division, but does use bit manipulation. I'll ask if it also uses integer multiplication, because multiplication by default comes in the same extension as division, but was also made available on its own as Zmmul. Bit manipulation instructions beyond basic bitwise logic are also their own extension B and its parts. Did the RISC-V processors used support these extensions, and if so did you tell the compiler to use them when compiling your code?

It's not that surprising that the winners are the ones with faster clocks especially when in dual-core configurations the second core is just set idle (why?) This test was designed to benefit single cored and higher clocked processors. Multicore processors are known to have better performance at much lower clocks frequencies and consequently more energy efficient. I'm having a very hard time to understand what's the motivation here. However, obviously the performance is never about a difference in ISAs, especially if all of them are RISC architectures. Put some CISC ISAs in the mix and you will see huge differences, though. Also chips that run at faster clocks generally consume more energy. That's the whole deal about multicore architectures, to have high performance with low frequencies. The whole deal of ARM processors and their use on mobile devices is exactly that. No surprise here either, since this is obvious. The only surprise is to see a processor running at 72 MHz consuming more than one at 160 MHz. I think this must come from the fact that you are measuring power at the board level, not at the processor itself, otherwise we would see this reversed. Now about RISC-V. There is no way RISC-V processors could compete at any level with ARM processors that have been far and wide used in smartphones. RISC-V processors are new kids in the block that are running far behind. RISC-V is still lacking the support needed to be better than ARM processors. But there is a huge advantage of RISC-V, though, that cannot be measured for now. It's potentially much cheaper to produce RISC-V than ARM processors, since it is an open and free ISA. However, we cannot still see the advantage in prices because they are still not produced in high volume. Volume production is everything in chips prices. But we can expect to see much cheaper RISC-V processors in the future to the point of beating ARM processors prices. I think that's where the RISC-V will position itself as a competitive ISA.

This is good for RISC-V. It is comparing ARM which has been around (and refined) for decades with RISC-V which is quite new.

The sp20.1 cortex chips are 1.7 times s.I.p. than the M.C.U. Chips even at vv3 dash 9

Garry, please, you;re killing me! It's ESPRESSIF, there is no X in there! XD

A decent video. And yes, instruction set architectures don't largely impact power efficiency. Hardware implementation however impacts efficiency far more. But there is nuances on the ISA level that sets limits for actual implementations of the ISA. Be it limits on minimum transistor count, power efficiency, peak clock speed, etc. Sometimes one has to trade one aspect for another. As an example, a resource efficient architecture using few transistors will generally not offer all that great peak performance. While a more peak performance oriented ISA will tend to be hard to build with few resources. Power efficiency is meanwhile largely decoupled from this view of complexity, since power efficiency is more about how well a given piece of software can make use of the architecture provided. It is oftentimes better for efficiency to have dedicated instructions for complex tasks, but what tasks to choose is a debatable subject in itself. If one throws in everything but the kitchen sink, then it is often far from trivial to make an efficient hardware implementation of it in practice. In short, designing an ISA is all about compromises to reach a prespecified goal. And then make a good hardware implementation of that along the way. Then it is up to the market to find/make applicable software for it.

Can't you measure the current directly from the VCC and GND pins?

Hello from Tennessee, Mr. Simms. Love your channel. Thanks for the video.

Thanks Gary for this wonderful comparison! Greatly appreciated!