Yup it's extremely click baity for geekz ))) would be fun if it was commonly click bait 🪤 : Stop the chip printers!!! Hyper NA confirmed 👌👍 Moores law going inter dimension 🚀🌌
As someone who's been following chip lithography for close to 3 decades: The next step is always "a major crisis". This started already in the early to mid 90s. And I think "we" learned from EUV to not put it off. That EUV was delayed by a decade just got the fabs to become insanely good at multi patterning. TSMCs N7 was an absolute bonkers smash-hit. It's only downside was that the hundreds of patterns made lead times enormously long. N6 uses DUV for almost everything, but has two critical layers moved to EUV. This, besides the small logic shrink, made it absurdly cost effective, and is the reason why AMD likes to do everything possible on N6. EUV vs High NA-EUV will probably be the same: They will figure out how to make sure they only use it for one or two layers in the beginning. If that's the action plan, then maybe a polarizing filter is financially viable.
While true, it is also clear progress becomes increasingly harder and more expensive with diminishing returns. And while many hard limits have been argued yet passed, this time we are faced with atom size. it is about time for something very different.
Indeed, we can appreciate it. It is deserved. Stirling work, as always. Knowing that he would always appreciate comments,though, Rayleigh is usually pronounced "Rally" in the English language. Yes, I am struggling to find criticisms of superb work.
At this point retrieving magic fairy dust from the martian moon Phobos would probably be easier than the best alternative, if the martian moon Phobos had magic fairy dust.
The more I watch, the more impressed I get by the people at Zeiss. They are literally like ok well, so we can't go the obvious route with bigger masks but our buddies at ASML need a solution, we don't care, we're Carl Zeiss, we gonna deliver. And ASML are on board putting all their trust into them on delivering. Breaking and bending the barriers of physics is just nuts.
Soo where is real technology at then? At the moment we are struggling to return to the moon yet apparently we did it about 50 years ago. I mean you have an interesting statement here, anything to back it up though? Can we do sub-nanometer or molecular size logic gates yet? @@rexxbailey2764
How can I go about becoming competent enough to work at ASML or a similar firm in the semi industry without having studied engineering/physics/math? I have a BA in History & Economics but have beeen fascinated with ASML and chip making for the better part of the last year and want to make a career pivot into the industry. Any advice appreciated, thanks in advance!
@@nicholasblake1392if you want a research job you will need to be competent enough to do research. Sadly without a stem degree you will need to have done insane projects on the side to justify being hired for that. You could become a scrum master or a manager of some sort however.
Do you want to become an engineer or someone on the business side? I suspect that there's need for people like you on the business end but not really on the engineering end. The factory floor may work depending on how much on the job training a company offers.
Yes! New video! You're cranking them out and I love every single one of them. Perfect mix of indepth dives into facisnating things no one covers and your humor adds a great touch.
Asianometry, your presentation digests the source material better than a cow's quad-gut. Thank you for your hard work and unflinching commitment to objectivity and references. Hit or miss, your vids I never miss, yea?
"Even being charitable with the trend, a Hyper-NA EUV machine can cost over half a billion dollars. That is about the cost of 1 Barcelona contract with Messi." This satire, unbelievable. Messi's contract costs are completely ridiculous. Keep up your work, it is fascinating.
That wall with Snell's Law on it is in Leiden, where the University of Leiden is located, and is one of eight located around the town. All of the formulas are from Dutch scientists, with the exception of one, which is Einstein's Field Equation. There is a website which talks about them- unfortunately I cannot link it here.
In this (still) Western centric world. The law of refraction should be properly described as Ibn-Sahl's law. Mr. Snell was a smart Dutchman, but with current history knowledge the title of discovery goes to Ibn-Sahl who described the effect quite a few hundred years earlier.
@@narcosalpha9472 Regarding Stigler's Law of Eponomy, I recently became aware that Morse Code actually was invented by Alfred Vail in 1840. The original Samuel Morse code had a moving paper tape with a number assigned for each letter, i.e. 26 lines for the letter "Z." The operator had to look at the tape, and then look at his notes, to write down each letter. Slow and tedious. On the other hand, Vail's system was incredibly fast and efficient, the dots, dashes, and even spaces all conveyed information. Vail used the sound of a relay clicking, with different sounding clicks for dots and dashes. The operator could concentrate on his notes, while listening to the clicks of the relay. Vail added punctuation, and made the most frequently occurring characters in the English language the shortest characters in the code. Vail was a partner in Morse's company, but Morse took all the credit for the code, and actually cut Vail's share of the proceeds. Vail then quit the telegraph business. "Morse" code is still widely used today by amateur radio operators, aircraft navigation beacons, and for identification of satellites, among other applications.
Except they aren't simple components. They're the most technologically advanced thing humans have ever mass produced. And they're only financially viable because they need to be produced in such bonkers numbers.
@@andersjjensen transistors are simple, and even making structures of atoms is kinda easy (done in the 70-80s), but making billions of transistors on a chip, that is made in millions is something unbelievably challenging
@@hhkk6155 Making billions on a chip with a defect rate so low you stand a chance of getting a final product is the real feat. But I don't agree that "transistors are simple". Even today the biggest hotshots in the industry are pouring ungodly sums into RnD in the pursuit of the perfect doping, the perfect insulator thickness, etc, to get the best possible voltage/frequency response with the lowest possible leakage. I mean.. transistors CAN be simple. Just buy a standalone BC547 and you get yourself "a transistor" cheaper than a lollipop. But building a discrete circuit out of those aren't going to net you something that operate above kHz. What I'm trying to say is that everything is simple if you "zoom out far enough" and gloss over decades of cut throat market pressure to do better.
FELs were proposed a while ago. Everybody was saying “it will be quick, easy and straightforward”. It wasnt. But I am still a big fan of this direction and hope that it will be the future
It's unbelievable how "normal" the results of these processes, that literally push the limitations of physics, are to us. We got microchips EVERYWHERE around us, yet it's so glossed over how insane the needed precision to make those is.
Amazing video as always. Just several weeks ago Zeiss shipped the first high NA optics system from Oberkochen, Germany to ASML. Weighing in at several times the weight of its predecessor and consisting of many times the part count.
Excellent video! I'm amazed at how well-informed you are on this subject! There is massive contrast enhancement using polarization for lines and spaces, but the tool will be used to print 2D patterns, not just lines and spaces. For 2D patterns, polarization is less important. Rigorous simulations have shown that polarization is not a problem down to about 10 nm half pitch. Using TE polarized light at the 8nm and 6nm half pitch nodes does gives some process window improvement for 2D patterns.
Excellent overview again, thank you. I feel we need to appreciate the metrology in this more. While that seems a meta discipline, without it this won't progess much at all - I'd guess metrology can be its own episode really. The positioning of chucks holding the wafers, the mirror handling robots and the vacuum vessels for running optics metrology needs to be as insanely precise as the steppers. You're moving pieces at speed and with sub-nanometer precision, which is just awesome.
Honestly, I love the content and the presentation tooo. But, half of the opitcal physics and the NA reduction affecting the quality of chips flew over my head. I'll have to watch this many times to grasp it. Anyhow, wanted to Thank you in words for the effort and time you spend in compiling and presenting such in depth content. May you continue to prosper this way and reach many heights 🙏
Higher NA means light comes at a larger angle (away from 90 deg) sees more of the grid/layer structure of the Masks, and thus the polarzation effect. That is how understand it at least ;-)
RIP Cheems, Im happy to have found this channel recently picked up Chris Miller book "Chip Wars" and have been intrigued with the subject ever since, something which shocked me was finding out that was at this level of lithography snell's law would be a factor in manufacturing, amazing.
Just the fact that humans have been able to understand how to orchestrate all this things (controlling light, laser hitting things, masks, resists, polished af wafers, clean environments, etc etc etc) to produce chips is incredible. The concepts alone I mean. But then the fact that they make it work 🤯🤯🤯
I'd say this is a nearly perfect vid except for the "in regards" but it's still an absolutely perfect explainer of an amazing topic. I realize I'm being pedantic but there's a chance you might appreciate it.
Hey Asianometry. Been a subscriber for a while and really like your videos. While watching this one I thought about how much I wish I could inform the young ones in my homecountry about these things. (I am Kurdish, but born and live in the Netherlands and have interned at one of your discussed companies!) They're so fascinating and I think it might even be an important thing to be aware of these advancements, maybe inspire whoever could come up with the next best thing. You really make it a story which is well put together and easy follow and listen to. How would you feel about translations in any way? Perhaps on your profile or re-uploads by anyone? Either way big ups man. also 12:17 was very nice, pulled me out of my nerd trance while also making me think I about how rough it is to realise technological advancements are deemed not worth it for the same price a football player purchase is cheered on. Not knocking football, it just is what it is. Good job have a great day :)
Can you imagine taking this video back in time 40 years and showing it to Intel? They would be working on their upcoming 386 microprocessor using a 1um (1000 nm) process.
I have plenty of thoughts like that :) For example, to show Rudolf Diesel, how modern Common-rail engines can insert 16 dosses of fuel per cycle, at ~4000 RPM, what power and torque they can generate. face would be insane :D
I wonder if having the "grate" oscillate during operation would help ameliorate the uni-directional issue. It's common practice except we call the grate a "grid" and it helps clean up those off focus photons and create a better image. I've been enjoying your presentations- esp. about the soviet union.
Thanks for all your great videos! Just wondering for the High and Hyper NA, what is the actual physical feature size it would be targeting? What would be the limit in feature size given size of SI atoms?
John, While I work within a modern data center, instead of MW, I’m going to do some math to represent my site’s energy consumption with respect to WalMart! Great video, my friend!
Very cool video. Any chance you could make a video on how the very first silicon-chip was manufactured? I'm curious about how engineers came up with the idea to infuse rocks with lightning to trick them into thinking.
Hyper-NA looks like something out of science fiction, mastery over the necessary technologies to do it will also doubtless be useful in other applications. It's always nice to see that Moore's Law might be alive for a few more years yet, might be the final push needed to have a lot of other consumer products/services pushed into the realm of feasibility like real time path tracing for games and high refresh rate 16 bit 8k micro LED screens.
Very good video, thank you. By the way, I found it a bit funny how you pronounce "Rayleigh": RAY-luh. The pronunciation as far as I know is RAY-lee, which is the way I've always heard it being pronounced by my English speaking physicist colleagues, but I guess yours is acceptable, though disconcerting because at first I didn't know whom you were talking about.
I think we should all just look at a freeze-frame of 10:56 for a few moments. Just think about what this represents... and that it's possible to do better. I love this channel so much. The most incredible technology the world has to offer, and explained in a way we can all understand.
10:50 For a second or so I thought you are showing the wrong image, until I reminded myself that the 3nm and so on process nodes have feature sizes 10x bigger. The process node description is based on the performance equvivalent of a CPU that came into being 20 years ago.
Hi, thanks again for the interesting video! If you have the time and interest, I'd really like to see a video on IBM's EUV processes and how they compare to ASML. Have a nice day!
If I had a few billion cooling in my check book, I'd be building a medium-sized synchrotron ring with the highest beam width and beam current I could potentially afford. 14/11nm light is basically at the bottom of the range for modern synchrotrons; the light is as close to monochromatic as you can get this side of continuous-wave lasers, the luminosities are quite literally stellar -- to the point where you can reliably turn macroscopic objects into plasma with a single pulse -- and the beam angle is so low you'd need a planetary sized ruler to see any divergence. Add to that the ability to fine-tune the laser frequency *exactly* to your needs and you have an ideal lithography light source. The only drawback is that it, by itself, takes a large aircraft hangar by itself and you *really* don't want to be on the same plane as the beam ring.
Hearing about this here first despite being in the industry (films not lithography.) Though I suspect that depth of field will be the real killer here for a lot of fans, as wafers get thicker and more vertically structured, because bow control and uniformity will become major integration challenges. It may just end up not being worth the cost when you have to correct extensively for bow and lose die to high wafer bow causing patterning issues or due to all the extra processing to correct the bow.
Another super informative video. Many thanks for all the incredible details. One quick note: NIST has published a bulletin listing all the units that definitely should not be used. Wouldn't you know it ... "micron" is on that list. 😮
Acceptable? According to whom? Joe Blow? The whole point of having a National Institute of Standards and Technology is to have ... wait for it ... standards. Quod erat demonstratum
i especially think that the fairy dust might actually be implemented - because its the most obvious choice and it will fix a few of the other problems, also
Given how far we made 193nm stretch I'm sure that 13.5nm will stick around for a while... if nothing else, there'll probably come a point where the per-machine output drop from multi-pattering becomes cheaper than yet another exponentially more expensive machine. Assuming we don't run into a wall that hasn't been accounted for. Given that so far, we don't even have a photo resist for High-NA, there's a very real possibility that a photoresist suitable for Hyper-NA doesn't get found in time for the rest of the process... or at all. We may very well be getting to the point where the molecules we need end up being too big for the maximum thickness of the photoresist layer, or something stupid like that. But that's the glass half empty point of view - I'm sure it'll work out.
It’s interesting how the mask manufacturers not wanting to increase their mask sizes moves the majority of the effort and finical risk off of them and onto ASML and their contractors like Zeiss. For the mask manufacturers, it’s a way to avoid risk but for the industry as whole, it makes the overall task of high NA seem much more difficult.
It almost seems that they need different mirror set up's inside this machine, to achieve their different depth and resolution applications per wafer. Multiple machine's inside one machine, probably the time it takes to process each wafer makes that economically unviable. Thanks for the update.
I find it fascinating that the maximum size for High-NA is much smaller than regular EUV. This property push designers towards chiplet designs. Especially companies such as Nvidia with their Tesla series of accelerators which has so far been around 800mm2 in size have to figure out how to make their designs more modular if they want to harness the potential of High-NA.
I wonder if we’ll eventually make an absurdly short wavelength FEL of high intensity, where the source will be so intense that we will be able to use refractive optics once again, and the wavelength so short that we manage to get a really good resolution from it.
Wow so many question which im sure have been asked, but with High-NA and Hyper what would be the transitor density, would love to see a video on this answer say for a Intel chip or Nvidia, maybe could cover the possible outputs in compute.
I was a bit surprised by a refractive index smaller than 1, as it would mean a speed of light larger than in vacuum, for that material. However, from the plot, it seems like it is a relative, not an absolute, index, meaning the ratio of the absolute indexes (i.e. referred to empty space): for instance ZrO2-MMA being smaller than 1 simply means that Zirconium dioxide has a larger index than MMA. Yet, as EUV is essentially X-rays, I don't know if it is possible that it is close to the resonance frequencies of many substances, in which cases, the absolute refractive index may be smaller than 1, but at the cost of absorption.
Kinda funny to see x86 speeding towards this wall while more efficient designs from ARM & RISC V mature as viable options for general purpose chips. Perhaps the future is in the art of mixing chiplets after all. GPU's seem to just scale to whatever power consumption they want, but a CPU doesn't have that luxury. What is more important, the process or the architecture? Can we just become better designers to make up for a future stagnation in process shrink?
The cost of a high-NA machine is not prohibitive. Consider that these machines are not making simple ICs. These are making ICs that go into graphics or compute devices with 2 - 6 billion transistors/IC. If the IC doesn't have this, there's really not a lot of reason to make the IC using a 2nm process node. They could use N5 as a more economical node or N7, and this is for ICs with many millions of transistors. We're at the point to where moving a circuit to smaller process nodes REALLY has to be evaluated. Even with nodes like N7 and N5, these are making high end compute ICs with a few billion transistors/IC, or die. So, moving to high-NA for one allows N3 to be make more efficiently and cost less to make. That's a REALLY good thing because N3 hasn't even hit the high end, high transistor count market yet. Right now that's being made with N5 or N4, and N4 is a variant on N5. Maybe it would be more beneficial to make even these nodes with high-NA but the yield rates are plenty good right now from at least TSMC making N5 and N4. N3 is still kind of the unknown right now because I believe for TSMC that's going into risk production for a couple companies, and then a little later in this first year run will even be Intel. Apple will of course be a first customer with this node and I don't know who a 2nd will be other than Intel but once again, I don't think Intel is coming in at the beginning of N3 production. AMD will be on N4 and N3 next year, so I think their production run should start around the end of this year. Apple ICs should be in production even now for N3. So, the reason why the cost isn't prohibitive is they'll be making ICs that companies charge a lot for, based of cost/sq. mm. It won't drive up the cost of say, AMD CPUs because you're also reducing the size of the IC, and I'm talking about AMD not Apple because in the world of server AMD is significant and Apple isn't. Apple is mostly making consumer products. AMD makes consumer and business products, especially high end server products, just like Nvidia does. So, through all of that what I didn't talk about is how today's CPUs are being made. AMD has already moved to using multiple chip design for making CPUs to run servers and home computer. They can already take advantage of the more expensive process nodes like N5 to make CPU cores, and they can take advantage of lower cost process nodes to make the parts of the CPU such as the I/O (input/output) for the CPU to communicate with everything outside of the CPU, such as a graphics card, memory, a storage disk, etc..... Intel is about to be doing the same thing. So they can deal with higher cost/wafer because they get a lot more ICs out of each wafer, and they can push certain functionality out of the core chiplets so they use as little as possible of the most expensive, smaller node processes like N3 or N2 when it comes out.
Hello Mr. Jon. Recently I'm hearing a lot of things about nanoimprint lithograhy. What's all the buzz? I guess only an episode from you can clarify. Your wizdom to show the light 😊
Alright not to nitpick, and if someone else already pointed this out I can't find it, but at 3:45 you say Zeiss built a robot, they built the cell (chamber door and vessel) ie the stuff you see right before, but the actual robot they use is an off the shelf fanuc, not anything special, you can even see blurry text on the joint 5 saying the model number. Now it's too blurry to read but I can assure that's a fanuc M2000iA. Specifically a fanuc M2000IiA-900 (900kg payload) which is actually the smallest of that series of robots The bigger models are used for lifting cars
One of the best producers on RU-vid. It seems asml and tsmc are chasing ever more near impossible and expensive manufacturing methods for ever smaller gains. Is there any alternative to this direction, theoretical or otherwise, as a dead end chip density gains must be approaching? What will the world be like if computers now, will be hardly any slower than machine made 50 years in the future?
So customers do not want bigger masks (likely due to cost) and end up paying for a far more costly tool chain in return. Penny wise, pound foolish if you ask me.
Tooling is highly reusable while the mask is consumable. Every new chip design needs several hundred different masks but you can reuse the EUV scanner.
@@kazedcat That is so, but as the video explains, each of those tools is highly specialized for just this process. It has a limited reusability in that sense as well. Plus there are changing demands for the masks as a result as well + new problems that designs need to take into account. It all adds up. A less complex solution / fix the root of the problem approach looks better to me.
@@TheEVEInspiration High resolution scanner are use for critical features but lesser resolution scanners are also use for less critical features. For example 7N process uses an EUV scanner for only the first 2 metal layers while DUV scanners are used for the rest of the 12 to 15 metal layers. The same thing will happen with High NA EUV. At first they will only be used for a few layers while Low NA EUV will be reused for the other layers. Then when Hyper NA becomes available the High NA EUV scanner will be reused for less critical layers.
