I don't know enough about how the MMU interleaves (or doesn't) memory in the STE to make any educated guesses as to the difference between four slots and two, but I would backup the sentiment that whilst if the TOS ram check fails, the memory is certainly not working properly, the converse isn't true. It will certainly report OK on bad memory in certain circumstances.
Yeah no idea. Id assume the RAM itself isn't interleaved inherently. In that it would use BANK0 2MB first, then BANK1 2MB after. But IIRC, TOS shifts the video address based on how much RAM it has. I am working on the assumption that more RAM takes longer to refresh. I guess I could measure RAS/CAS with 2 and 4 simms to see if the timing changes.. Might give another clue.
@@exxosuk It would not surprise me from a load balancing view if, dependent on the ram config register settings, the MMU took even longwords from one bank and odd from the other.
@@exxosuk I'd be surprised if it takes longer to refresh with more memory. There are separate RAS lines for banks 0 and 1 and each slot has its own CAS. They could all be refreshed in parallel. TOS will put the screen buffer at the top of whatever RAM it detects. It's entirely possible -- I'd go so far as to say likely -- that the STE configures 0x0 to be across the bank 0 slots and 0x04 to be across the bank 1 slots if 4MB is detected [nb. not literally 0x0 and 0x04, mind, as they're mapped to ROM, but YKIWIM and I thought it would be more confusing to give 0x8 and 0xC as examples!]😜
