Building CRC Hardware using Internal Linear Feedback Shift Registers

Подписаться 26 тыс.

Просмотров 3,2 тыс.

50% 1

A cyclic redundancy check is easily implemented using an internal linear feedback register. In this video, we begin with a review of the CRC, show how it is implemented mathematically, and present the hardware with which it can be done.
Timestamps
00:00 | Intro
00:18 | The problem with datasum-based checksums
01:41 | Quick CRC review
02:59 | Demo of how CRC and modulo are related
08:22 | Appending remainder to dividend to make final data stream
14:03 | Demo of two bit errors detected with CRC
15:04 | How Exclusive-OR works when computing CRC
16:32 | How to use a shift register to calculate CRC
Hashtags
#lfsr #shiftregister #crc

Опубликовано:

28 июн 2024

Ссылка:

Скачать:

Готовим ссылку...

Добавить в:

Мой плейлист

Посмотреть позже

Комментарии : 2

@shloper 3 месяца назад

I would be great if you can comment on how these packets being sent/received are organized

@shloper 3 месяца назад

Hi! Thanks for the video. I have a question about the flow: For an N- bit message and an M-bit divisor. 1. The N- bit message is being sent over the course of N clock cycles. Simultaneously the reminder is being calculated in the TX and in the RX. 2. After the first N clocks the TX trasmits the M-bit reminder. At this point in time, the LFSR in the RX should have the same reminder as was calculated in the TX. What happens on the RX side at that moment? If we stop shifting the LFSR and capture the next M bits of the reminder we will be able to compare them at the end of transmission (N+M cycles) to validate the correctness of the TX/RX. I didn't understand your comment at the end about how to verify/use the reminder that is being sent after the message. Thanks!