The reason your SRAM had the same value, on every single power up is actually very interesting (and useful). Due to manufacturing differences of each chip, when powering up the cells will be metastable, but settle on a value (0, 1). This will often be the same for each cell, but not all, as some cells are more random. This can be used to identify each chip(with some error correction), and is actually used in hardware authentication.
Excellent video. I found it very clear and informative. I acquired a box of ic's from a friend a few years back, hm6264 ram amongst the lot. Trying to learn how to make it useful, potentially as part of a digital direct synthesizer.
The first video I see from you and its great. I learned a lot, thanks. At 1:07 I'm not sure if it should mean "...so it takes a little more current" or "a little more transistors" maybe?
I googled 'ASC62256 FPGA' and I got your video. Thank you so much! I hope it's not too late to catch your attention and ask a couple of questions. Is the address bus really bidirectional? I'm reading the data sheet and I see that the chip requires 5V Vcc. Could you recommend best practices/support circuitry when interfacing this RAM chip with an FPGA (Cyclone 2 EP2C5T144C8) at 3.3v? My FPGA edu board has a 5v supply but the I/O standard on the pins, supports '3.3v LVTTL' and '3.3v LVCMOS' Thank you, again.
A bit of a late reply, but the address bus from the memory devices perspective is not bidirectional, it is input only. If you take a look in the datasheet you'll probably find that the Vih of the inputs are TTL compatible (i.e. 2.0V+ or thereabouts), so driving it with LVCMOS at 3.3V will be fine. The data bus is of course bidirectional, but you could interface the FPGA with something like a 74LVC245 running at 3.3V because the LVC series (largely) have 5V tolerant inputs when operating at 3.3V.
Really informative thank you also just humble question; can use 2 of this ic in parallel like all addresses togther and the data separately to have 16 bits of data and 16 addresses...I tried it it works but the 16th address doesn't work any idea...or how to will be appreciated
I know this is a bit late but are the strict timing requirements for write cycles common to all similar chips? I found a datasheet (also alliance memory just a newer version with the same pin out)) for a 15ns chip and it doesn't mention it.
I was wondering what kind of memory I need to use for my synthesizer I'm designing to store settings and this is one video I found to help me out and I'm glad I found it because it really helps me better understand which is and does what and what I can use for what purpose. Also you look super cute, when do you get off and whatchu doing later?
Thank you very much for this excellent video! I wan't to interface STM32(F/H)7 micro to a FPGA and this is something I will watch a few times. I need few quadrature encoder counters, eight of them and this is something I need to figure out, e.g. how to interface CPU to the FPGA and read and set quadrature counter registers.
Robert Baruch i get it from here. www.google.com.vn/url?sa=t&source=web&rct=j&url=ecee.colorado.edu/~mcclurel/Cypress_SRAM_CY62256.pdf&ved=0ahUKEwih94bn5tzVAhUBybwKHf5cAqMQFggsMAQ&usg=AFQjCNHJIVZmDhF2OBQqhJwXTu1-7iSrPg
