CRAFTING A CPU TO RUN PROGRAMS 

0s and 1s? Too much abstraction. You better start learning how the MOSFET transistors route current through capacitors and diodes

Really? You write code in binary? Liar.

I totally get it. I'm a frontend dev but I'm fascinated with lower level code. As soon as you get into decoding Bluetooth streams or parsing protobuf bytes or if you do anything with WebAssembly, it becomes pretty clear that JS just wasn't meant to handle those situations.

Same here!

Epic!

Thank you so much

great game

Thank you, need to check this out

Thanks ❤

Thanks for sharing!

There is another ... It's called The Why Files.

if you can use your fingers to perform counting math, you're good enough to understand this video's content. and i am not joking. computers are actually idiots counting using their fingers, they just do it insanely fast.

​@@lis6502 yep I agree

Another great place to start is watching Ben Eater's 8-Bit Bread Board CPU series.

To be able to increment a register in the file, the 6502 has hidden input register in front of the ALU. ARM2 has a write-back register behind the ALU.

Generally true, but that also depends on the convention one uses. One can use low and high clock pulses for different tasks which is typically referred to as the rising and falling edges, but you also have high and low logic too. So, in general, there are 4 possible variants to choose from, consider the following table: Clock Edge | Logic Type ------------------ | ------------------ rising | low rising | high falling | low falling | high This is something to be aware of. One always has the rising and falling edge of the clock pulse to work with, but as for Logic Type or convention, the main distinction here is mainly the difference between using NAND based or NOR based technologies within the construction of Sequential Logic (memory-based components). Some latches or flip-flops can be constructed using NAND based components while others can be constructed using NOR based components. The main difference between the two, is when the Reset lines of these latches is being asserted. Now, the vast majority by convention typically chooses NAND over NOR because NAND is cheaper as it does require less Transistors to construct as well as requiring less space in its layout design. This doesn't mean that NOR based logic doesn't have its uses. In some situations, and devices, NOR might be preferred as it does depend on the nature of the problem and the context in which it is being used. So, in general and in most situations, we typically or for the most part use the: NAND variant. Now as for low and high logic in conjunction with NAND and NOR based components, we can always convert one to the other. You can have a purely NAND system working in its natural based logic, but you can also configure it to work in its opposite variant, and the same can be done with NOR based components. It's just that the conversion process does require more logic to be thrown at it. But yes, memory access with read and write operations that trigger their control lines is determined by the rising and or falling edges of the clock. Yet, there is another component that is vital to this and that is the Edge Detector. Without the Edge Detector the rising and falling edge signals of the clock pulse would be basically useless. If one cannot determine if the edge is rising or falling, then the entire discussion of setting the memory's control lines is kind of moot. However, not all but many memory devices have their own edge detector built into it internally. So, in many cases we can abstract away from this, yet that's not always the case. Some memory components don't have any edge detector, and in those situations, we do have to roll our own for without that edge detector, the clock pulse is meaningless.

@@skilz8098 there is a great write-up of the clock in the i386. Basically, there are two kinds of clock lines routed across the chip. Their signal is inverted. Rising and falling latches are grouped so that we don’t have to pay twice for the “last mile”. At least on this chip ( or any microprocessor I looked at ) there is no edge detector. Just the flip flop is switching from input to feedback cycle. So it captures its current value on the edge of the clock. The edge does not need special properties. It can even bounce as long as the input value is stable during this period. I wonder if we could reduce noise on the power lines with a three phase clock with one inactive at a time. All rise and fall switches are balanced and don’t introduce common mode noise on the power supply. So sequential logic would have 3 groups of latches. Two of them pass .. ah crap. One of them passes through the signal. At all times at least one latch latches.

A shift “register”. So still a register. The AtariJaguar actually can read two values out of palette SRAM at the same time. The processor writes the output into the linebuffer ( another SRAM ).

Main reasons for using registers are speed (to avoid slow memory read / write operations) and to increase the compactness of the machine code (to avoid specifying memory addresses which can be up to 64-bits long). Historically, all sorts of CPU designs existed. Some stored almost all registers in memory (such as TMS9900), and some partially (6502 "zero page" can be viewed as 256 external registers of the CPU).

Also, adding an ALU access to each memory cell would drastically increase the circuit size with very little benefit compared to the cost. Memory size would decrease by orders of magnitude even if you just connected every cell to an ALU, not to mention the problems in doing so for non nand based memory.

Your assumpion about "memory is slow vs registers" is not applicable to the example of CPU architecture in this video. Memory here is the same pile of transistors as a registers. The only difference is a set of wires.

Yeah people forget that while the 6502 has only 8 data pins, internally it has two data busses ( okay, data only, no address) which can be parted to have 4 in total. The partition border is (can be) between the ALU inputs. So you for inputs you would need to pick registers from different halves of the register file. This is the super cheap CPU from 1975!

Reg-mem instructions were actually quite common on CISC. 68k for this reason has 16 bit instructions. 6502 used the zero page of memory a lot. The clean approach is to use 8 bit offsets. So you have a base pointer ( into an array, heap, or stack ) and use a literal offset to access fields. ( or branch around in code ). The nice thing: load is just a normal instruction. Still Store is the weird one.

I mean, a lot of home computers and consoles had multiple memory chips. I always feel like it is a design failure .. So a mem-mem instruction would always move data from one bank to the other.

@@ArneChristianRosenfeldt these machines had PLAs and MMUs doing heavy lifting of juggling the busses and providing enough of abstractions for chips not to collide with each other. Your thinking has fundamental flaw: mem-mem instruction would always move data from one bank to another THEN AND ONLY THEN if these memory banks would be only chips attached to said bus. When you have to arbitrate between multiple nodes wanting to share their results or tackle upon new problem you have shitload of switches to correctly flip to isolate two and only two interesting parties on the bus at the exact moment of data exchange between them.

@@lis6502 I was kinda spreading my “wisdom” across many similar comments. Many people don’t seem to know how complicated memory access is in a real computer. Just do the math: each bit costs 6 transistors in SRAM and 1 transistor plus a huge capacitor in DRAM. So a C64 with 8kBit chips has more transistors in every memory chip than in any other. So they are expensive and of course designers try to utilise them to the max. MMU is something I don’t really understand. I think that N64 was the first console to have it. Amiga OCS and AtariSt don’t have it. But then again, to select a chip on the bus, the most significant bits of the address need to be checked anyway. So you could have like 16 chips selects which can be mapped to arbitrary pages in memory. So like in NEC TurboGrafx with their 8kB pages to ROM? I thought that the PLA does not cost time because it runs parallel. It is just there to not enable write or read at the last possible point in time.

Exactly as I thought, but I think the problem is storing the result

Also realistic access to memory uses address registers. So you don’t actually cut down on registers. I think that the 6502 zero page is a mistake. In the NEC turbo Grafik CPU, RAM, and ROM all cycle at 8 MHz. No 8 bit CPU after this. But at least for 10 years external memory was fast enough. The MIPS R1000 uses external SRAM caches at CPU clock. Intel was afraid of using pins, and MIPS has 3 32 bit data connections on their chip? Third is to DRAM. The power goes somewhere: electro magnetic interference.

Yeah, why did Intel offer a chipset for their 8008 where one of the chip converted a single clock to two non-overlapping pulses. Their first CMOS CPU the 386 had a well localised circuit on chip which created two non-overlapping balanced signals. These basically act as the power supply to inverters. Inverted power blocks on the diode. So either feed through xor feed back is powered on the flip flops.

8087 stack does not reside in memory though. It’s not a separate chip. But then again I guess that it is more optimized towards density than speed. 80 bits in 1981 !!

I wonder if on the Amiga it is possible to time the start of the micro code execution of DIV or MUL so that the 68k gets totally of the bus while for example the graphics DMA runs?

Ah, context switching!

@@skilz8098 the context is “microcode”. Your third paragraph. What does microcode bring to the table when no one else uses the bus in the meantime? Microcode already gets instruction fetch from the bus. Why also remove data access? JRISC for example use micro code to implement the inner vector product as reg-mem.

@@ArneChristianRosenfeldt Well, in modern CPUs - architects and computer systems sure you wouldn't be wrong. Yet, if one is building their own system from discrete logic gates or ICs, they are literally hardwiring the buses, the bus transceivers, decoders, etc. and they have to measure or be aware of their clock signals and even the strength of their signals. It all depends on which route of path they tend to take; they could build out all of the logic for their decoder or they could just wire it to say an EEPROM and program it with the binary equivalent. When I started to implement Ben Eaters 8-bit Bread Board CPU in Logisim. I had to build out the components (registers, logic, counters, etc...) for the control unit. Ben did all of that on the bread to where they controlled the I/O signals coming out of his EERPROM ROM module. Here is where my implementation slightly varied from his. I ended up using Logisim built in ROM. I ended up writing a C++ application similar to his EEPROM C like code to generate all of the binaries. Then I had to take the printed output from my C++ project and had to message it (trim off all white spaces). Then load it into the ROM Module within Logisim. This was also tightly integrated into a second counter for all of the micro instructions. Not for every single main system clock cycle itself, but for every increment of the program counter, there were up to 4 or 5 sub cycles. This secondary counter on a varying repeatable loop managed the fetch, decode and execute cycle. Some instructions only took say 3 cycles, where others took 4 and some took 5. All of this had to be taken into account to instruct which device to either accept or assert data from the bus. It was a single bus that handled, instructions, addresses and data. It was a system wide shared bus. So, again, it also depends on the overall layout of the system. It depends on its architecture. Sure, a modern CPU or system doesn't use a single bus anymore, and for most tense and purposes even at the assembly level, we don't usually concern ourselves with the fetch, decode and execute sub cycles, but we should still be aware of their mechanics and properties. Take an NES apart and trace out all its paths. Or take apart an Atari and trace out all of its paths. Get really creative and take apart an Arcade cabinet and trace all of its paths. And that doesn't account for all of the processors, coprocessors, and microprocessors within those systems.

@@skilz8098 what is modern? 6502 is from 1975 ( 70s I am sure ). I think that it predates the SAP-1 book. 6502 solved the variable length of instructions: there are end instructions in microcode. Some illegal instructions manage to miss those and freeze the CPU. Wiring of clock signals is important in ICs. For example up to 1985 commercial chips only had a single metal layer. So any crossing needed a bridge through highly resistive poly-Si . The clock distribution network on DEC alpha is so powerful and has so wide conductors that it is clearly visible in the die shot. They were clearly pushing the limits. SAP uses adders, but I read that you could buy TTL ALUs in the 60s . Dataport 2000 and other processors even operated on single bits (Usagi has videos). Discrete Multiplexers and shifters must have been cheap . But then, the C64 first started with memory with a single data pin. Maybe dataport used those or those early Intel rotation registers which acted as main RAM. I like how Atari and Commodore insisted on tri state address pins for the 6502 CPU. So indeed everything sits on a common bus. Same with AtariJaguar. N64 has a point to point connection between the custom chip and this RAMBus to the DRAM chips. Arcades are a bit like a PC : lots of expansion cards on a mainboard. Not optimized for cost not energy efficiency. Though some are straight forward: buy the expensive 6809 and a lot of RAM for a double buffer with many colors. This much RAM filled its dedicated board on its own back in the day and is obviously expensive. How do low volume ROMs work?

I would love to see a steampunk demake of an instruction scheduler. I like the instruction queue in the 8086. Now let’s take the 4 Bit ALU from the Z80. Then let’s try to occupy memory io and ALU and two port register file access every cycle. No global flags, but RISCV branch instructions.

1) the MIPS 5-stage pipeline was invented in 1980. The inventors observed that real programs need addressing modes. So access to RAM reads the address register, adds some offset using the ALU, sends the address out to RAM, and gets back the result in the next cycle. This works for ROM and SRAM ( think: Commodore PET or a console like pcEngine ). DRAM at the time already multiplexed the address bus. So it (could) take two cycles just to transfer the address. Also often in the first cycle some external component checks, which memory chip should be enabled: ROM or DRAM or some IO chips? 2) No. All CPUs have CMP and TEST instructions. On RISC there is the zero register. Starting with SH2 the flag output is optional. 3) On a computer with multiple components which can write to RAM, the registers are your safe space. Many computers had DMA read out for graphics and sound, but the Amiga introduced a blitter which would write to (chip) memory. Sega genesis could have conflicts between Z80 and 68k. 4) That's why instruction encoding is so inefficient on CISC. At least 68k has 16 registers and the swap instruction. Why did people not swap register banks on Z80 that often? Always want to stay compatible with interrupts?

How would you execute a program? You go through it line by line. Like playing music or reading a text aloud word by word.

I'll be showing this to your professors

They are just registers. I always thought that the accumulator in 6502 is smarter, but it turns out that it can only calculate decimals, which is useless in games. JRISC on AtariJaguar gets slower if you load two registers. To keep things fast, reuse the result of the last instruction. There is a hidden accumulator. Actually, there are two. Another one for MAC.

Two port memory is actually available. Then noobs will say that the price is the concern of the BA, while senior engineers know about the cost of all the addressing on the chip.

Huh? 4 bits is the base organisation of SH2 . Also SAP-1 as shown by Ben Eater. 4 bits allow you to store signed shifts for 8 bit values. 4004 and binary packed decimals. 16 color graphics.

Is this type of operation supported by modern assembly languages in any way, or is it a hypothetical architecture feature?

@@EMLtheViewer It was just my suggestion, i dont know. I researched the topic and did found anything, so I my probably wrong. But I do know that in grafikcards, you can load an array of data in one instruction.

@@EMLtheViewer The 6502 has Increment and Rotate instruction which act directly on memory, and I hate it. But ROR was too much? Or a second accumulator B. But did you know that the 6800 did only have one address register and could not efficiently memCopy?