Mate, over 40 years ago I started out (after a bit of Fortran IV and SEL assembly language) on 'pipelined micro-code' for a 'Floating Point Array Processor Unit', which was about the size of an upright freezer, and I believe was sold by a company called "FPS Systems", and had a whole 32,768 words (each 32-bit plus some floating point stuff) of memory, and it had a five-stage instruction pipeline. It was intellectually the most fun I've ever had.
At 17:07 you mentioned that when lw follows sw, there is no data hazard. But the value to be stored will be stored at the end of mem stage. While that value will be required during ID stage. If it takes garbage value in the ID stage then it gets actual value only y forwarding. So it is ultimately a memory data hazard. Please explain.
in the first example after reading r1 from sub instruction we could have again read r1 value from sub only for instruction AND,OR why agin read from starting ADD instruction.
design the following set of instructions using a 5 stage instruction pipeline. if any hazards occur, identify those hazards and redesign the pipeline for rectifying each hazard. find the number of clock cycles taken to complete the following sequence of instructions. assume all stages take one clock cycle each to complete the operation. a. add r2, r1, r0 # r2 ← r0 + r1 b. mul r4, r3, r2 #r4 ← r3 + r2 c. sub r6, r5, r4 #r6 ← r5 + r4
