Decoupling capacitors 1/3 - Local energy storage devices 

Thanks for the shoutout.

Great approach and execution as always!

I love your videos... It s a shame you dont have more viewers.....

I am glad I found your channel

Best explanation I've seen. Thx

This is the best video about decoupling capacitors. Thanx!!

Absolutely facinating. Thanks for breaking that down for me to be so easily understood.

Thank you, exelent video, love to learn something new!

Can't believe I missed these gems. Great mini- series to teach something to someone at every level. Awesome Fesz, thanks man.

great explaination love the spice simulation , keep up

Thank you for Sharing , your video has always bunch of information. Keep uploading.......

Excellent tutorial with great practical advice.

An excellent explanation. Let me add that total inductance (L) of the cap also depends on the way it is connected to the power & return planes. In partcular: How many vias are used (the more, the lower L), how large the vias are (the bigger, the lower L) & how far the planes are from the cap (the shorter distance, the lower L).

Excellent work! Keep it up.

The current (sinusoidal steady-state) in a capacitor is due to the resultant electric field E_net (resultant of the applied field and an opposing electric field, the fringe field). If the capacitance of the capacitor C is made large, then the fringe field does not build as fast as it would have if C were to be smaller. With a large C, the charge sprays on the plates do not result in developing a large voltage in a given interval of time as evident from the capacitor voltage-charge relation Q = CV. The fringe field is smaller and the net field consequently is greater. Therefore, at a fixed frequency, the current increases as the size of the capacitor is increased. The current also increases as the frequency is increased. So, we say it passes higher frequencies of applied voltage. If the frequency is made smaller, the fringe field builds very rapidly and in the limit when it is dc, it blocks the applied voltage. If a resistor R is connected to the capacitor then the resistor limited current is not enough to dump charge fast enough at such high frequencies and of sufficient quantity to produce any significant opposing fringe field. Therefore, for a given RC combination the output voltage picked across the resistor is able to reproduce the input signal with less attenuation. We say that the capacitor bypasses the high frequencies …..in reality, the electric field of the input voltage passes “through” the capacitor with almost no opposition. This makes the capacitor useful as a coupling capacitor for ac signals in amplifiers and also as an emitter bypass capacitor in transistors that will afford larger output swings by reducing the amount of ac signal feedback without affecting stabilising dc feedback. It is not possible in this post to discuss in more detail current in capacitor circuits and capacitive reactance. Electrostatics and circuits belong to one science not two. To learn the operation of circuits, Current and the conduction process, resistors and how discussing these topics makes it easier to understand the principle of superposition of potential which is a direct consequence of the principle of superposition applied to electric fields, watch these two videos i. ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-TTtt28b1dYo.html and ii. ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-8BQM_xw2Rfo.html The last frame of video 1 contains in the References articles and textbooks which discuss the unified approach. Sections 3.1 to 3.3 in Chapter 3 of textbook 4 discuss the operation of the RC coupling circuit with sequential diagrams using the unified approach. Also, Section 3.6 in Chapter 3 of textbook 4 discusses the operation of the bypass capacitor tied across the emitter resistor using the unified approach with the help of sequential diagrams in a transistorised common-emitter amplifier.

Great explanation. I would like to add something: make sure that you choose the right package for your capacitors. For example: if you have 3 decoupling capacitors (1u, 0.1u, 0.01u), the biggest value should come in a big case (let`s say 0805), and the lowest value in a small case (0402 is fine). This way when the frequency increases the impedance drops to a point and than starts fluctuating around that point. If all your capacitors come in a 0805 case, the impedance would keep rising after that point.

well prepared and presented.

This helped out a lot. THX

Nice explanation

The best! Thanks for sharing!

Thanks, well done!

Excellent

good channel!

nice, very nice

"hello... and welcome back" Wait what ? SUBSCRIBING !!!! 😂

Insightful. Thanks a lot

I wish I had teacher like you when I was doing Electronics graduation.

I put a like without to see the video. i know it is very good.

Hi...i am not able to simulate ciruit with inductor because it gives under shoot of around 2 kv .plz help me as i have spend whole day in it. I domt know what silly mistake i am making . May be current pulse setting plz attach ltspice software file of circuit or tell me about current pulse setting .plz help ASAP PLZ PLZ PLZ

Hi , according to v=L*di/dt -> 2µ*1A/2n =2kv the voltage supposed to fall -2kv how in the LT it is full only to 0v ?

At 4:15 the voltage drop appears at approx 400us, but the pulse statement delay field says 1m?

Where do you come from? I just can't guess it from your accent :)

Hello! When you show and explain something on the screen (for example LTSpice), the viewers eyes are glued to the screen trying to go comprehend what is beeing explained at this very moment. But then you very often suddenly switch to face cam, which is too abrupt and distracting for me, because I was still trying to see whats going on on the screen. So my suggestion is, that you do not switch camera focus while there is still something on the screen. Or maybe implement the facecam as small picture-in-picture. I hope I explained it sufficiently, also that said, I thank you for the videos!