Yes, but doesn't fully shield the H-Field component unless it's a special mu-metal designed to do that. Nickel screening alone mostly works on the E-field component, but only has about 1/100th the permeability of MuMetal so it's not that great on the H-field.
What’s really hard is trying to shield low frequency signals, it was once described to me that trying to stop 50/60 Hz is equivalent to trying to stop a bullet with tinfoil. High frequency of hundreds of MHz or GHz that a modern laptop would produce can be pretty much stopped by nearly anything in its path.
npgatech it’s not just black magic to some of us, it’s black magic to ALL of us lol... there’s principles you should follow, but a way to engineer this problem out of existence would be impossible, it’s so dependent on each design. I’ve had job interviews where the chief engineer would desperately ask if I had any EMI compliance experience, because they had failed the test so many times and didn’t have a clue what to do about it... if you end up with a product that’s badly misbehaving it can be a real nightmare even for professionals that specialize in this type of work... the problem you will face is not learning the techniques, it’s the massive expense of it; it’s stupidity expensive to test EMI, and without testing you will have no idea where you are. You need really expensive gear just to start asking if your efforts did anything at all...
I am a PCB designer in a small electronics designing company and we are aiming a lot on the low price, so most of thw stuff we do is 2 layer. It caused a lot of problems to us when we go to EMC testing. Biggest problem is the fast switching, you can put 10R to 22R resistor in series in the high speed traces, this helps a lot. Also keep your traces as short as possible and always look for the ground loop.
Yes, it is an excellent idea to put small resistors in series with the IC outputs that drive high speed traces. This helps control the edge rates, reducing radiated emissions. It also reduces the current spikes as the high speed outputs drive the capacitive loading of the traces, vias, and other IC input pins.
The resistors typically allow you to match the impedance of the trace. This stops current sloshing around hence lowering emissions. Think of a wave in a bath of water. Now put some form of blockage in the path and you will see ripples all over. This is what impedance mismatches are. You are trying to make everything look the same to the wave fronts. A better analogy is your tyre across a dirt road and the suspension. Fill in the holes and you creat a smooth surface, or remove dirt piles and create a smooth surface.
@@ZeusandHades You use a Signal Integrity simulator tool. This calculates the impedance of the trace based on the characteristic impedances of the materials of the PCB. Ie using microwave stripline and microstrip modelling. You could do it by hand too (as we did in the old days) using microstrip and stripline formulas (there are books and internet resources - ARRL HAM manual has a lot of info in). Tools such as Altium can do this for you too but for better quality Mentor/Siemens Hyperlynx and Cadence’s Allegro SI package. There’s also Ansoft RF tools too and a few others.
To be more accurate you use IBIS models Io Bus Interface Standard which also models the Inputs and outputs of various ICs on your board. This allows you to simulate the whole signal chain and the trace and figure out the correct termination scheme. I will add that this can be fairly complext to get right if you are working on SerDes or other very fast signalling technologies. It’s a field in it’s own right.
This is so nice to see the effects directly and the difference between 2 and 4 layers. I made a lot of PCBs for my DIY projects that are using radio connection. I always had problems with the radio module because the SPI for that was very "sensitive", but once I place that on the exterior of the PCB and made a ground and Vcc plane, the board had no more radio errors. Especially that my board was using PWM signals and MOSFET control and that made a lot more noise. Thank you for all that you show us!
FCC Part 15 is the compliance regs in the US. In the late 70's these new personal computers (Apple II, CP/M systems, but NO IBM PC, yet) plus video game consoles, and other microprocessor based products needed to be added to the compliance standard. So subpart J was added. The whole Part 15 reg has been since realigned, so there is no subpart J anymore. I'm old enough, and had was in the electronics business when subpart J was added. The company gave me the task of making sure our product designs complied with the new regs. Some of these RFI/EMI testing houses are better than others. The first one we went to just ran the test, and we had to fix it back at the shop, before retesting. Another house, let us try things while at their facility, and ran shortened tests to check our intermediate results. They also gave us suggestions. That was a good test facility ! Now products come out of China, and testing boils down to applying a compliance sticker.
Of course testing is still required, but is it actually performed. The thing is when Chinese products are sold directly to customers on websites like eBay, then the testing might be just a sticker. The importing party is responsible for compliance, and when this importing party is a end-user who doesn't know or care about compliance, then the Chinese manufacturer wouldn't bother performing tests. When I have a company importing Chinese electronics and reselling them, then I must be sure they're complaint.
GromBeestje That’s a downside of importing items. If it has a compliance label then it also has an associated number that you can check. Some stuff I have seen has no compliance at all, or only domestic compliance (which may be tighter in some cases - particularly when you have Trump toadies in charge of compliance). Retailers are always liable for what they sell, and certainly here items are anonymously bought by compliance authorities and sent to labs for verification. If they don’t comply then the retailer must recall the item(s). I’ve seen it happen with appliances a couple of times, and often with infant and children’s clothing and the like. Regulation is a necessary part of a functional society.
heh. I have a lot of old game consoles and computers around, and it's interesting seeing the progression in the shielding. Also the history of some designs. Like the 800XL vs it's predecessor from 4 years earlier. Mostly the same internal components, but the shielding... The early 80's variant has some pretty hefty metal shielding inside the plastic outer case... But the late 70's variant is basically all metal construction with an additional, very thick inner layer of metal just for shielding purposes. Because at the time it HAD to be to have any hope of meeting compliance standards, yet a few years later near enough the same internal hardware could get away with comparatively flimsy and insubstantial shielding. (still extremely heavy shielding compared to more modern devices though.)
KuraIthys It’s more a case of not knowing how to meet the standards, so ensuring compliance by excessive shielding. By the early 1980s it was easier to include EMC compliance testing in the R&D process.
I'm an electrical engineer and I love these type of videos. I'm still pretty young a very hungry and eager to improve my skills. Work for a large company and so there are other engineers whose careers have been dedicated to Signal integrity. So I don't really get to learn this as they are the ones who are the real experts on these topics. Then again I don't think we've ever done anything smaller than a 6 layer board. We ground flood the top and bottom layers and all signals are inside the board. That's how they deal with Emi and EMC. They just surround everything in ground. Please do more videos on practical engineering tips and tricks. I enjoy these types of teaching the young engineers much more than I like an unboxing video. I do really like your tear-downs to as they can teach a lot
Just dropping in to say how refreshing it is to see a content creator who actually interacts whit their viewers. I barely understand any of what I'm watching, but as a hobbyist going nowhere I still find it all super interesting.
Good work Dave, amazing video. I have never seen a 2 to 4 layer PCB comparison before, and to have a board for the test with this level of complexity is really a bonus.
Great job Dave. I love your video not only the technical aspect, but the way you spit out your knowledge with so much emphasis. Keep doing more and more video.
Great credit to Dave for going to the effort of making this board and exhibiting the measurements! Some of Dave's videos can be relatively blab or rant oriented, of which there is much on RU-vid :-), but videos like the current one really distinguish this channel. Well done Dave!
This was super helpful! Thank you. Short loops, via stitching and watch out for bypass caps. Perfect timing for a current project as well. Still killin' it after all these years!
Awesome video! Seeing a side-by-side with identical boards with different layers is something that many of us have never seen done. Quick question: What would the difference be if you reversed the layers and did the traces internally and the ground and 5V externally? Thanks so much for your efforts, Dave!
@@EEVblog I would love to see that. Also, what effect does placing a ground "ring" around the outer perimeter of the board that attaches to the device connector shields and then attaches to the board ground plane through capacitors? I know that technique is for ESD protection, but does it help to reduce EMI at all? If you want to see an example of what I'm referring to, you can look at the BeagleBone PCB files. They have that "ground" perimeter on every single layer of the board, not just the outer layers that connect to connector shields. Does that have to do with the high-speed DDR or HDMI signals that are on the board?
With a board with 100% through hole components, not much difference except for the better shielding of the signals that now are inside a shielded box (planes on the outer layers). In a board with SMT components it makes a big difference, since having ground/power internal layers means they are almost a complete plane with no voids, while if they are on the outer layers, you have all the pads of the SMT components creating voids and discontinuities in the planes which reduce the effectiveness of the planes. But if you are really concerned with emissions and you have money to spare for a couple of extra layers, you can fill top/bottom layers with ground (only if there is another solid ground internal plane) plus ground ring on the edge of every other layer and use lots of vias on the edges of the PCB to make the PCB like a shielded box for all the signals in the internal layers. Mentor Graphics wrote a book about how using top/bottom layers as ground helps to reduce the number of layers (on board with 16+ layers) since it means bypass caps don't need a via to ground (otherwise every bypass cap has a via to power and one to ground). Also the pair power/ground planes creates a capacitor which is part of the power distribution network to the high speed chips. Changing the position of the power/ground planes in the PCB stackup will change the capacitance and the inductance. FPGA (or other highs speed ICs) companies have lots on apps notes on this topic.
Ground planes are a must for high frequency digital designs, but I was not expecting such a big difference for these low frequency boards. Pretty instructive, thanks for the video!
Do you have any opinion regarding the pros and cons of having 4-layer boards with the power-planes as the outer layers and the signal tracks on the inner layers, versus having the signal tracks on the outer layers and the power-planes on the inner layers?
@@MaxWattage 1. Propagation delay is higher for internal layers. 2. You'll need a ton of vias, that would break up the ground/power planes and that wouldn't be great for return paths. Also reducing vias on high speed signals is desirable. 3. It would be difficult to rework the board if needed.
@@EveryThingTechet Points 1 and 3 you are correct. Point 2 is completely wrong. It wouldn't make any difference to the number of vias. You could simply swap the layers but still use the same artwork. You could actually REDUCE the numbers of vias by using blind/buried vias which you can't do with the signal layers on the top and bottom.
@@mrgibbo63me46 nah it really would increase via count. Depending on the board, you could add a ton of vias. Some signal traces wouldn't normally go into the middle or bottom layers, but to make a ground plane on the outside you'd have to add 2 vias per trace.
@@TheRealMonnie Definitely true for an SMD design. Through hole like in this video - the layer orders would not affect via count. You want the power/GND layers to be close together though - increases capacitance between them. There is something to be said for having further GND on additional outer layers and the Faraday shield effect. High speed data is often sandwiched between 2 GND layers to maintain transmission line impedance.
This is great, the first time I have ever seen someone do this on the same pcb as a 2 layer and 4 layer with groundplane. Thanks Dave this is a really really useful emc video.
Thanks. Can't say I've seen it anywhere else either which is why I was interested in doing it. Perhaps another video with a 6 layer version with ground planes on the outside layers?
EEVblog You video should be used in electronic schools! Why not make the top and bottom layers ground with the traces and power layer internal? Would that make it super shielded?
@@Daveyk021 lol. Maybe it would. On the other hand, having had to do amateur fixes to old electronics at times, the thought of having all the critical traces being internal within the board kinda gives me nightmares... Multilayer boards in general can be a bit intimidating when you're trying to figure out what the circuit looks like from the PCB traces alone. When large chunks of the traces are effectively invisible... Well... Yeah. Good luck. >__
Regarding the heatmat, a rather different ("real") kind of heatmap I have seen many years ago in a video (that I can't find): The guy took some thin layer pcb ground planes (full, with split etc.), painted them black and took some prepreg with signal traces, overlayed them and then ran high power high frequency signals through them. In the end he took an image with a thermal camera. The result was very neatly showing how the low frequency components chose the intuitive shortest path, but the high frequency ones were following the signals, or spreading out in places nobody would have thought of.
I love your explanation about near and far field extra to the main subject. When it comes to layers, I newly redesigned an RF board (up to 6 GHz) from 4 to 6 layers. A lot of other changes had to be made, mostly because of the last problems with delivery of the components and because of the heat issue. But I have taken care of the appropriate routing of the RF lines and of grounding in general, in the same time REMOVING many decoupling capacitors (after watching Eric Bogatin presentation at Altium Live) and... the PLL on the board is soooo less noisy!! The biggest Spourious reduced from ca. 30 dBc to less than 50. Sadly I could not compare the grounding alone so nicely as you did
Yes please on more EMC / EMI videos, especially radiated. Basically what you can and can't get away with in a design and pass compliance testing. And what you can and can't derive from a semi-affordable pre-compliance testing setup. Examples of topics I'd love - I'd especially love to see comparisons between lab measurements, DIY antennas and middle road spectrum analyzers like your Siglent and Rigol, DIY OATS , the probes as you did in this video, semi-anechoic chambers, and *especially* with TEM cells since they're supposedly usable in lieu of a proper OATS. How to properly setup and run the equipment to test against compliance standards for intentional and unintentional radiators.
I was thinking about that before he mentioned it, definitely would be neat to setup a rig for that. Kinda like a CNC machine and you put the board in and it just slowly tests each spot. The same rig could perhaps also be used for taking very high res photos of PCBs. Imagine doing something kind of like google maps but with PCBs.
Yes, I was thinking a printable detector for a 3d printer, Dave did say he was going to show how to "roll your own detector" now we could print a clip on case that attaches to a 3d printer head like my creality ender 3 and boom a few hours work and you have a very high spec 3d EMI scanner! the ability to create 3d plots would be of immense use for problematic layouts and great ones too, the ability to log the EMI values in 3d space will lead to all sorts of clever solutions... just a brilliant idea.
It also raises some interesting points too, like getting the DUT to behave in stable consistent way over time, as the scan progresses you don't want the test device changing power levels or turning on and off antennas etc.
What a coincidence, I was just watching the older video of Dave working on this board in KiCad. Just as I finished, got a notification for this one... sweet.
Make more stuff like this! There is so much stuff we are told about PCB layout best practices that we take for granted but an engineer doesn't have time to make all these mistakes for themselves.
One of the main parts of my Ph.D. was looking at the comparison of EFT performance between two and four layer PCBs and how they affected micro controllers. Took physical boards, tested them, and then was able to simulate their characteristics. "An investigation of the EMC properties of modern microcontrollers", thesis available in the British Library! If you have to use two layer boards best to have ground on both sides, and flood as much as possible between signal lines. Lots of vias to stitch those layers together. Think low impedance! Think of making any ground path as short as possible around tracks, around ICs and their decoupling. Don't be afraid to use capacitors, and even bulk capacitors further in to the board as a well of power! Don't just think of having the power supply at one side feeding everything but by using those bulk capacitors to have localised reserves. So if your power line has gone deep in to the board don't be afraid to add another electrolytic to reduce the impedance of the supply at the far reaches.
I LOVE when you do EMC Videos.... My companies units need to be compliant to EN12895 for our systems. I found using a Walkie Talkie is an excellent way to perform some precompliance Radiated Immunity Testing. You should try it out Dave.
Interesting. FWIW, a coil like that measures the magnetic flux though the coil, so when the coil is flat you're measuring the vertical component of the H field.
An interesting measurement would be to take a bare (unstuffed) board and measure the capacitance between Vcc and Gnd to find out how much filtering it would be.
Great stuff! I've tried to find information on the internet, but there's so much conflicting information on doing good PCB layout. Videos like this really help. More, please! How about splitting up four layer board ground for isolating sensitive areas? Can't find any reliable info on how to do it. Some recommend star ground, but I never manage to figure out where to put the center node for best effect. Anyway, thanks again.
Frans de Bruijn Looking in random data sheets for this is going to be hit or miss, as different writers and skill levels will be used from one datasheet to the next.
@@johnfrancisdoe1563 The datasheets often show the component layout with ground isolation for components that have both digital and analog components. T.I. has the board layouts for their evaluation boards available for download, thats a good start to see how they do things. There is also some software called AppCad that you can use for calculating the impedance of tracks if you want to design controlled impedance boards. this is especially important when you are working above 20mhz clock speeds.
The information is conflicting because people try to compress a complicated subject into simple rules of thumb and this rarely works in EMC. As for splitting ground planes, I'd try to avoid it. It can have benefits, but the risks are much bigger and it's full of traps. 9 of 10 times a single uninterrupted ground plane will be best. As for information online, check out Henry Ott's website and the book EMC for product designers.
Loop area is critical. But there can also be resonances, which can actually amplify harmonic noise. So, solid ground and power planes and a good assortment of decoupling caps is the way to go. FYI, I recommend you take a look at K-SIM at Kemet.com. It's a handy free tool for choosing your bypass caps. Shows a nice Bode plot.
What’s a real pain these days is getting power consumption low while not having ridiculously fast rise times on the board, thankfully most hyper fast signals can be held within the small confines of the ICs themselves or we’d be in real trouble. Impedance matched low voltage tracks with pre emphasis becomes hard to avoid.
Great video. A couple of questions: 1) On a 4-layer PCB, is there any significant difference between a SIGNAL-PLANE-PLANE-SIGNAL and a PLANE-SIGNAL-SIGNAL-PLANE arrangement? 2) Are GND+GND and GND+VCC planes equivalent? My guess is that: 1) PLANE-SIGNAL-SIGNAL-PLANE would be slightly better for radiated EMI because it traps the noise inside the PCB, but that also means it will slightly degrade the signals. 2) Shielding would be equivalent but GND+VCC planes would be better than GND+GND as it lowers the impedance on VCC nets, also the GND+VCC planes would form a wide bypass cap which might help at very high frequencies. Any thoughts? edit: Just realized several people came up with the same questions :)
You missed the *3rd* orientation by having the probe vertical (looking at the video). It might help to determine if a problem is with horizontal left right traces versus vertical up down traces.
If the shorter path has lots of vias the current distribution might not be that obvious, as it favors the path of least impedance, whereas vias can have high impedance for higher frequencies
Back in the 80s I had a TRS-80 model I, which did not have true audio output. There was a program that got around this limitation by intentionally generating EMI that could be picked up by a radio placed near the computer.
One of the earliest things I was taught for circuit board layout, mid 70s, was to first layout the vertical ground and power traces in parallel right next to each other and going right underneath the chips. This was to keep the length of the ground loop for the chip and bypass capacitors as short as possible. Next, on the other side of the PCB you placed your horizontal power and ground traces at the end of each chip. If you had a long package, you could disrupt them but it was preferred not to. Those were tied with vias to the vertical ground and power traces every place they crossed. Thesy always ran from board edge to board edge. Next you laid out your highest speed switching traces first so that they were the shortest length possible. You're pre-planning when you chosing chip locations on the board was to get the chips involved with these highest speed traces as close as possible to each other.
Haaaaa the joys of EMI compliance. Love the Tekbox probes I have the same kit with a Siglent SA3021X spectrum analyser, awesome for the price. I also built clamp on RF probes with ferites (Wurth electronics makes great ones) works great to measure radiated emissions from cables and see the difference cable impedance can do. Today there's no reason to not do EMI pre compliance testing in house, it saves a bunch of money and time.
Test house charge excessive amount of money and time to test a board. I'd rather use cheap tools like these to asses my board's EM characteristics.. Thanks for the video Dave and hope you will make more on videos on tackling EM at design phase.. maybe start a new project and show decision making process at each stage of PCB designing..
Dave - You have concentrated about 15 years of school of hard knocks learning into a 36 minute video. If you do PCB layout and you have to get PCBs tested, all of these topics you will eventually have to consider and deal with. The DaveCad explanation of the the E an H fields is spot on. This is a great introduction of how antennas work and you can begin to see the effects having objects in the near field of an antenna. I have done most of my work doing RF design and layout. I began to be required to outsource the layouts and got some odd looks when I wrote out a list of layout requirements for the person who was layout out my designs. One requirement got a ton of pushback. I required that every power and ground via be doubled on the layout. This has many effects. The first is that it halves the impedance of the connection to further prevent noise generation. Secondly, it allows for simple identification of via locations on the pcb as the power and ground vias look different from normal signal vias. There are so many other little rules that are required to make the odds of a design passing EMC they are exhausting to think about. No unterminated stubs, don't place inductors near sensitive traces, if you do, make the layout orthogonal. Place inductors at 90 degrees to one another in filters. Traces always traverse pads. The order in which parts are laid out in a filter matters. The list just goes on and on and on.
Exactly the same as on that silent terminal, where you had the massive copper bodge wires to make loop area small on the plug in daughter boards, as the original ones had a long snaking ground path around the perimeter of the board.
@@EEVblog Yes, thanks. I did buy a FFT module for my Tek TDS3054 scope so I am equipped. It may be necessary to buy the preamp and "sniffer" probes like you used.
In really fast edge rate electronics we used to run traces between two ground layers (gnd/trace/trace/gnd) just to control the trace impedance better. I was fortunate in that I rarely had to worry about EMI because the enclosure was fully shielded. Used to run vias around the perimeter to control the emissions sometimes.
I have made some RF designs using PCB for in the 1-2 GHz range and the method we used was to use an entire GND plane or several layers with GND and other layers with RF using microstrip. But in order not to have RF signals propagate via the GND planes and the Power plane, the Power plane was not filled, only traces with decoupling caps at either end, to make it work as a lowpass filter i.e. shunt C- serial L - shunt C. Would be interesting to see if that made a difference to the EMC of that PCB you made. Great video by the way, Really liked it! More of this stuff please!
Need to split ground planes for e.g. analogue and digital processing on the one board. Not to mention high voltage stuff! Ground loop is your friend if you treat it well.
Great Video Dave! What a fantastic job, doing a complete layout and board to being able to do the comparison! I don't agree with you though that it is a "huge difference" with 10 to 15dB. But then again I'm an RF guy that often work with ranges of 100dB or more in signal dynamics. Again, great work!!
With 4 layer boards, there's often a much bigger gap between layers 2/3 than between 1/2 and 3/4. But power planes work best when they are tightly coupled with each other. So, assuming you did L2 ground and L3 power, you would have benefited from keeping the copper pours and tying the pour on L1 to power and the pour on L4 to ground. This would increase the interplane capacitance between power and ground significantly, and with proper stitching it would also make it much easier for signals on L4 that reference the power plane to transition to L1 - because the return current can ride along a power pour, instead of searching for a bypass cap so it can switch to referencing ground. For the truly paranoid, you can put the planes on the outer layers, and it will act like a pseudo strip-line. But in that case you REALLY need to have pours of alternating polarity to the reference plane, because the interplane capacitance will be greatly diminished if your planes are L1 and L4. Rick Hartley has a lot of very nice videos if you want to explore this topic in more detail.
I've done one for conducted mode emissions. I might do another one on mains conducted mode as I have some kit for that. But radiated requires a decent antenna and either an OATS or chamber, or at least something half decent.
@@EEVblog I just passed EMC compliance testing for FCC in north america last weekend. I had some issues with the 200MHz region on my board just over the limit so I tried some bench top probing like in the video with no luck. No matter what I changed, little difference was seen. The issue was the external connections to the PCB were acting as antennas, transmitting trash. A few properly sized ferrites and I was able to obtain one class lower then was the original target.
Coming back two years later to see if there was ever a follow up, cause it was super relevant at the time! Nope. Nothing. Anyways, my mantra in college became "If you can understand it drunk, you can understand it sober." But to this day, I can only understand Laplace transforms after at least 5 beers
If emc is the reason for using a 4 layer board, why not put the signals on the middle two layers? Put the solid power layers on the outside. Yes, you lose some of that free decoupling you would have gotten from sandwiching the power planes closer, but the two layers survived without it, so it's not necessary.
You can improve the ground by adding a few stitching vias even though the through hole devices provide this. Moving some traces to the other side to allow room for the ground helps also. Sometimes adding more vias to a route allows more room for the ground. A 2 layer board is harder than a 4 layer.
Loop area is so important👍 Grounding the can on these big old crystal cans helps a lot. Ground on layer 2 and supply on layer 3 is good. PCBs are fabricated with largest distance between layer 2 and 3, so using signal layers on 1 and 4 for signals keeps them close to the AC ground. Think microstrip, which is valid at the harmonics. Power and Ground should have enough decoupling so they are a low impedance between them so are both AC ground.
Please show ways to measure "far field" in a regular lab. Obviously less precise, but much more useful than having to take prototypes to a rented specialist lab.
Hi Dave, Nice education video and thumbs up. For me, this video has been an eye opener, how layers with power plan make difference in EMC ! Could you pls also let us know, how about having a single layer PCB? - will it generate lower or higher EMC? Any actual comparison please. I usually work with two layers mostly and single layer in some cases. It gave me a learning to follow the datasheet for the EMC sensitive components, where they recommend to have a separate plan and also no power trace underneath the chips etc. Now I understand it better. Thank you once again for this video.
EMC compliance testing isn't always in the far field. Most of the time it is but some standards test lower frequency H-felds (loop antenna) or E-field (typically 41" dipole antenna) in the near field. Military and some aviation is famous for this (E-field) however some rail standards as an example test H-field. Dav is correct about nearfield probes not directly correlating to lab compliance but targeting big peaks or broadband is always worth while prior to hitting the compliance lab. Just don't forget the cables, sure the emissions are conducted onto a cable however this cable will radiate, potentially greatly.
Its nice to see this is sort of regulated. Good to know, that they have at least thought about limiting such things. I wonder what sensors humans have made, to detect stuff?
You would get better results if you put GND planes on both Layer 2 and Layer 3. Vcc can be placed on Top and Bottom layers. It seems that there is place for it.
The 4 layer board shown has the power/ground planes in the middle. What would be the radiated difference if it were reversed, with signals inside, and power/ground outside? I admit that debugging the layout would be terrible, but once it is working, would it make a difference to reverse things?
First thing I thought when seeing the layout of the 4 layer board ;-) Will be quite interesting to see the difference it makes! Let's take a wild guess: another 10-15dB?
Expect it will give some improvement as the signal traces will be in a faraday cage. In practice this would be of limited relevance since with SMT the component pads are on the outer layers, and you don’t want to add vias for every signal pin....
i remember being able to hear my Amstrad CPC464 on FM band when loading games!..i guess it was due to be cpc being built as cheap as possable without any sheilding what-so-ever!
Thanks for this, I've now got a better grasp of loop area! I love designing boards. Nothing serious, just for my own purposes. A lot of them have constraints of either size or shape since they're often retrofits, so ideal layout is sometimes not possible. But I'm always looking to improve my layout quality even if I'm the only one that'll ever use my boards.
I think 2 layer boards are still good if you don't have particularly fast signals and remember to consciously limit rise times. New chips tend to have fantastically short rise times which may not be necessary for the application.
Nice and informative. From a problem solving and mod perspective it's good to have the traces on the outside, but from a shielding perspective then I suspect that having the ground and power planes outermost would be the way to go. Anyway - this computer is pretty neat and comparable with the Sinclair ZX80 from an educational perspective.
Great video, I would be interested in seeing a comparison of the 4 layer, ground power on the inner vs the outer layers - I _vaguely_ remember reading sections of Henry Ott's book on the matter some years back - I seem to remember that burying the signal on a 4 layer board gave slightly better performance but made the layout less ideal. Going up in the layers then gave more options with better performance. When we've sent boards for review to Telit (3G/4G modem) they always recommend signals on the inner layers but I always wondered how much difference it actually made on a 4 layer board.
To further improve the performance of this board, how much would copper pours on the outside layers help? In example Top: Vcc and signal Inner top: Gnd Inner bottom: Vcc Bottom: Gnd and signal Lots of vias everywhere I changed between Gnd and Vcc to further increase capacitance / reduce inductance (the latter probably will have a greater effect)
