Ep 080: Data Registers and the Program Counter (Instruction Pointer) 

Hi! I hope you are doing well. Xan you help with something?

This is not actually a branch. What I suspect you're seeing is the effect of the pipeline. If you watch Ep 085: Introduction to the CPU Pipeline, you'll see that the instruction being fetched is usually 2 or more addresses beyond what is being executed.

@@Intermation Ok wait. In that case i had a misconception of how a instruction is executed. So let's say that we have those three adresses: 0x00000040 | 1A000001h ; LDR BNE 0x00000052 --[this address is in executing state] +0 0x00000044 | E0000000h ; LDR AND R0, R0, R0 --[ this address is in the decoding state] +4 0x00000048 | E8BD8C70h ; LDR POP {R4-R6,R10,R11,PC} --[this address is in the fetching state] +8 ( PC ) 0x00000052 | E59F1018h ; LDR R1, [PC,#24] ... So does this mean that the instruction on address 0x00000040 is actually executing when the PC has reached address 0x00000048 ?

Yes, that’s exactly it. There is hardware set up to avoid executing an instruction if either the address 0x00000044 or 0x00000048 contained a branch instruction. That would cause a flush to the pipe line. In some cases, two pipe lines might be used when a branch is encountered. Now if it’s the case where the instruction at address 0x00000040 is a branch, both the instruction in the decode and the instruction in the fetch stages will be discarded.