FPGA PDM Microphone 

Hi Manuel, I'll start with the CIC - the input of the CIC has a minimum of 2 bits (width of data) because is taking signed samples (on two bits you have the range from -2..+1) so you have map the output from the microphone 1 and 0 to values to values of -1 and +1 in order to be compatible with the CIC (exactly in the same way you can map them to 8 bit to actual values of -127/+127) because AXI interface works in chunks of 8 bits. (btw when you use values lower that 8 bit chunks on AXI you need to make sure you sign extend your values) The remapping mechanism from 1 and 0 to 8bit signed (-127/+127) does both ie. converting unsigned 1 bit samples into 8 bit signed values (two complement format) this can be done with a mux (in VHDL/Verilog) Let me know if you got it. A

@@adaptivedesign8795 Yes thank you! That cleared up my confusion.

@@adaptivedesign8795 I also wanted to ask if you can give an overview of what the phase_inc block that you have does and how you implemented it so I can do that in verilog. This is the block that sets the phase increment of the dds compiler, I see it in your block diagram in the video where you show the 144mhz transmitter. Thank you.

Glad you like it!

My pleasure!

@@adaptivedesign8795 hi, where is link to sources?

Hi There, The pdm output is one bit but on each stage of decimating and low pass filtering (inside the stages of CIC filter) you'll have a bit growth so you end up will a much slower (sampling rate) signal but much wider. The "secret" of the PDM signal is that it contains you audio signal in a very fast digital (noisy) signal with the property of all the noise being located at higher frequency, By decimating and low pass filtering we get rid of the noisy part and remain with the audio component (or band).

@@adaptivedesign8795 thanks for your response so basically if I have a 3 Mhz PDM signal and if i want to have a 8 bit pcm as output , theoretically would be like waiting for 2^8-1 pulses of pdm and in base of the ratio of 1s over total length the pcm data would be defined so if my deduction is correct For 1/3Mhz * 256 would be considered the signal for 1 sample so the pcm sampling would be 1/3Mhz *256?

@@fc3fc354 That's a very simplistic way of describing it, the bitstream is getting decimated by a large factor 256 (if my memory serves me right) but every time you decimate you need to low pass filter the signal, hence the use of CIC which is perfect for this application because of the large decimation ratio. However nothing will stop you counting the number of 1s and 0s over a 256 bit window and slide that window. if the number of 1s and zeros is the same that's 0V,. if all bits are 1 that's your positive max if no 1s (all are zeros) that's your negative max. My guess is that you'll still need to low pass your new signal for the audio band. this could be an idea for new implementation.😀 your new sampling rate will be the original / 256 (so every 256bit in the PDM stream you'll have one PCM sample)