You are connecting the shield and GND with a small capacitor BUT doesn't you also need a large resistor in there like a 1Meg in parala with the cap? also do these things also apply for PoE designs?
Hello. It really depends on space and budget, IMHO. Jacks with magnetics are more expensive and larger. I've opted for no magnetics at all and a bunch of tvs diodes everywhere. Once again a very instructive video.
Nice video! I noted a couple of issues with the example project. The capacitor should be rated at the same voltage potential as the Magjack, which is between 1.5kV and 2kV. They're typically quite large. Also, the chassis trace on bottom layer can couple into L5 since they're probably only separated by 4mil or so, and there needs to be a 1mm clearance rule between chassis and GND for the same reason. A 1.5kV flash test with a PAT tester will show that.
That's a good point about the trace for sure, normally if I have to do anything with chassis GND I just put the ring around everything and pass it through the layers, then the clearance rule will take care of it. It's easy to forget about that one when you use traces for the connection.
@@genisuarez9463 I'd need to rewatch the video, but I think that's the one. As a rule, any capacitor across isolated/non-isolated parts must be rated to withstand the isolation voltage rating.
One question: With L2 having a chassis plane option (6min), "term" block (on L1-signal) is over L2-GND plane area or is it over L2-Chassis plane area? in other words, which plane is under this block on L2? which elements are L2-CH achieving? I haven't seen it clearly. Second question: You say that bob smith termination has a Cap rated at 2KV to the chassis GND. And you also say that chassis GND could be tied to system ground using a capacitor between chassis and GND?Are you talking about 2 different capacitors that should we need or are you refering to a unique capacitor?
TI Ethernet PHY PCB Design Layout Checklist says: < No metal should be under the magnetics on any layer. If metal is needed under the magnetics, it must be separated by a ground plane at the least. Metal under the RJ45 connector with integrated magnetic is allowed. > Wat would be the "metal" here ? If its not copper, chassis ground plane ? .. My stackup is signal/Chassis/chassis/signal under the integrated connector and thus traces to LED's and TVS diodes on the 4th layer near the connector board edge. This is not great for selective soldering assembly but there is no space. According to TI, I could opt to change layer 3 to GND but not sure that will cause SI issues. P.S Pulse has a nice document for PHY layout.
In this case "metal" could mean "anything that is not a system ground" so it could be power polygons, signals, etc. In general you should also not use a chassis ground as the ground plane for signals on the PCB. You can have chassis ground on the board but it should not be used to carry capacitively coupled return currents. The reason is that the chassis ground should not be used for a return path at all. Instead the chassis ground is just the chassis in the enclosure, at most it should just be a ring around the edge of the PCB as I've shown in another video on ESD.
If you're referring to bridging the chassis ground and the system ground, typical value is about 1 nF, this is enough to provide bypassing for high frequency noise. However, chassis ground is not normally connected to the system ground especially when magjacks are being used. You will see the capacitor used in this way to assist the return path when magjacks are not used. In my opinion it is much better to just use magjacks. If you're referring to connecting the connector shielding to a chassis ground, you can use a capacitor but best option is to use a direct connection as well as TVS diodes on the traces. If a capacitor is used, typically someone would follow some ESD-based guidelines to select the capacitor because the connector bodies will be exposed to the external environment. Typical value might be in the 1-10 nF.
using the cap is not a good idea. If an ESd occurs on the chassis side the capacitor will guide it to the PCB ground since ESD spectrum density is in range of some hundred MHz
I should have explained that some more. Since that connector is metalized you have to ground the connector housing somewhere, in this device there is no chassis ground and only a system ground. This is typical if you do not have a metalized chassis or an earth connection somewhere. Chassis is preferred though, especially in networking equipment. There are also cheaper plastic enclosure devices, these don't always use magjacks and will have plastic RJ45 sockets.
Hi Zach, If I am considering about the higher isolation from the RJ45 primary side to the secondary side, but noise suppression is not the first priority. Should I still just use the single grounding strategy? Does it split chassis ground and DGND achieve higher isolation?
Splitting chassis GND and DGND is meant to set the chassis as a safety ground that diverts any ESD-induced current away from the main system and the components. If you do not have a chassis in your system then you have no choice but to use the single grounding strategy, or you have to have primary and secondary side grounds but not route any other data lines between the ground split. For the main data lines, the isolation has to do with the magnetics termination. Ethernet links have a minimum isolation requirement that they must comply with, so the connectors and magnetics components that are used in these channels must provide isolation at least at that minimum value.
PoE can be used with magjack connectors, some connectors are specifically designed to support PoE, one part number is Bel Fuse 0826-1X1T-GH-F. Just make sure that the connector is compliant with the specific PoE standard being used in the device, this is because different PoE standards like IEEE 802.3af or 802.3at have different power levels that they support, and the connector construction must also support those power levels.
