HackCPU Logisim Clock Acceleration 

In preparation to build a VGA display interface using Logisim Evolution for the HackCPU, I encounter a stumbling block with the clock. I solve the problem by modifying the Logisim application to emit HDL as part of the synthesis process to synthesize a faster clock for the Xilinx series 7 chipsets.
Resources:
github.com/log...
mitpress.mit.e...
digilent.com/r...
github.com/chu...
github.com/log...
github.com/log...
docs.xilinx.co...
You will need the Vivado product from Xilinx to synthesize the design for the CMOD-A7 board. It's huge, but free (if you give your information). Sorry. I did not write it.
www.xilinx.com...
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