Thanks for the explanation! Would be great to see AD integrating these calculations at least into the stackup solver, as it seems like it's got all physical parameters required for such calculations defined as a stackup. Even if not automatic, but simply as a tool to have handy when setting up all those length-matching rules.
It does have all the physical parameters for this approximation, so you're right it could conceivably automate that simple calculation. The problem is that as soon as you try to control the via impedance with any nearby ground vias, you change the propagation delay for that via. Bringing in some GND pour on another layer that doesn't match the main antipad dimensions also changes the delay. Controlling via impedance is not normally talked about, but that via's L and C values calculated in the video do give you an impedance if you take the square root of L/C.
Automatic via delay calculation should be made possible. Add via fill/plug material (via plating, plug dk value etc.)to the via properties. Layer stack and material properties are already there. Why bother with entering the values yourself? Board layout software should be developed like a 3d game engine, then you will have all structures present in 3d for simulation/calculation instead of pseudo 3d (2d with additional parameters for thickness). Just as in Hyperlynx you will have to let the toolling know what type of signals (rise/fall times, frequency, amplitude etc) are present.
When Altium calculates overall trace length it adds a proportion of the via length based on the layer stack settings. If length matching is used for DDR then via delay is not required but package flight time adjustment must be entered in mm or converted from ps.
Totally grateful that you answered my question in such a detailed way! Thanks! I have one question regarding the anti-pad diameter in the single-ended example. In practise, what is the anti-pad exactly? In my designs I usually remove unused via pads on internal layers, so would the anti pad just be the diameter of the GND plane clearance around my drilled hole? So if I had a 0.45mm pad via with 0.2mm hole and my design rules were set to have 0.2mm copper-to-hole clearance, my D1 would be 0.45mm, d would be 0.2mm, and D2 would be 0.6mm?
You're very welcome. In your example your numbers are correct, the antipad is just the diameter of the hole around the via in your ground plane. With your numbers I get L = 1.4 nH and C = 1.05 pF, and the result is 38.4 ps delay.
Just remember, that was for routing across the entire stack. If you're only routing across two layers, like in a board with thin laminates going from surface to L3 for example, the delay will be much lower, maybe 7 or 8 ps depending on length. However, if you did that then there would be a stub. Then you could use that Dk effective value to calculate the frequencies where resonances occur and create strong insertion loss along that route.
hi, I have a question, In the DDR4 routing chip manufacturer suggests using the Z-axis delay feature in Allegro software when routing the DDR4 signal What's the equivalent solution in Altium? do I have to use math or is there any third-party tool to calculate delay, especially for DP for different layer stackups?
There is not an equivalent delay calculator feature in Altium. I do not know the accuracy of the Allegro solution, if it is based on an equivalent circuit model then it will be incorrect. But they likely took the solution from Sigrity and used that to determine the vertical via delay, or they might do it based on adding up the delays in each layer.
Well that 43 ps is an estimate for routing across the entire stackup. If you were routing a couple layers deep you would maybe have 10-20 ps depending on layer thickness.
