@Anastasi In Tech - What about using i-squared-l logic and/or vacuum channel FETs, possibly on chiplets? I2L seemed very promising when first introduced, but it's power consumption was high since transistors were all large at that time. As a bipolar technology it will not suffer from gate leakage problems. Are there any other reasons why it might not work? As for "vacuum" channel FETs, they are 10 times faster or more, partly because they use free electrons. They also benefit from nanoscale features, are extremely radiation resistant, and they can operate comfortably at temperatures up to hundreds of degrees Celsius. Also they don't actually require vacuum when built at small nanoscales.
@@fluiditynz - I left my comments and questioon here because it is the most likely place for her to see it. Nothing to do with the laptop she's promoting.
When I first started programming, and RAM was off chip and typically a few KB, we'd spend a lot of dev time working out how to do as much as possible in as little RAM as possible and as few clock cycles as possible. These days the demands to cut development time and get new features out, more driven by senior management and Product Owners than by real customer demand, seems to have ditched those ideas. If it's too slow the customer is expected to just buy a higher spec machine and new developers are taught ways to shorten development time but not execution time. I think that this is a false economy. About 10 years ago I was able to shorten a big data-processing job from 3 days to under 20 minutes, on the same hardware, by applying the techniques I'd learned back in the 1980s to key functions. It took me 5 days, but when this is something that has to be run every week the saving soon stacks up
You are absolutely right. Once I participated in a service job to get a power station running. The problem was to bring the gas engines up and running as fast as possible. After a few days the programmer had been flown in and looked for alternative assembler commands to save a clock cycle here and a clock cycle there.😁
Wirth's Corollary to Moore's Law: Any improvement in Hardware performance will be negated by code bloat at an equivalent rate. Kinda like traffic in London.
It's not a false economy, just a different emphasize due to the change in price structure. In the old days, memory were expensive, so we tried to economize its use. Today's memory are so cheap, that software developing time has become the most expensive part of a system.
@@gorilladisco9108 the cost of memory is largely immaterial. It’s the cost of execution time. Say you’ve got a transaction that currently takes 10 minutes to complete but if the code was optimised would take 7 minutes. To optimise the code would take the developer an extra 5 days effort and the developer earns £30 an hour (that’s the mid-point for a developer where I work), so that’s about £1100 wage cost but once it’s done that cost is done. Once rolled out the application is used by 200 people paid £16 an hour (I have some specific applications we use in mind here). Saving 3 minutes per transaction means either those same staff can process 30% more transactions or we can lose 60 staff at a saving of just over £7000 a day. That extra development time would repay in a little over an hour on the first day and after that would be pure cost saving.
You really have a knack for making complex topics engaging and easy to follow for everyone! Breaking down the challenges of SRAM and introducing phase change memory in such a clear manner is no small feat. Excited for more content like this!
The point "good endurance 2*10^8 cycles" prohibits its use for cache memory. But it's really a viable and competitive option as a replacement for Flash memory!
I'd be curious about the thermodynamic side effects of phase change memory during transitions as the crystallisation would release heat while amorphization would be cooling
The problem with chiplet design is heat management. Since every layer is active, it burns energy and produces heat, and this isn't good. A secondary problem is the bus interconnect because stacking requires shared lanes, so memory layers are in parallel, making the bus interconnect a bottleneck. Last but not least is signal strength and propagation time: stacking layers requires precise alignment and add electron jumping around, so there's a potential limiting factor in electron propagation, noise and eventual errors. This isn't much of a problem if the system is built around it, but it still is a limiting factor. There are solutions: since there's one master and multiple slaves there's no risk of collisions and so you can make a lot of assumptions on the drawing board... but busses are going to become wider and more complex, and that will add latency where you don't want it. My 2 cents.
- I wonder if they run veins of metal in between the layers to send the heat to radiator. - They put L3 cache on the second layer, which by virtue is quite removed from the logic circuits.
Thanks. Amazing video. It's kind of interesting how it always comes down to the same principles. First shrinking the size in 2D, then layering stuff, and eventually going into the 3rd dimension. And when that reaches its limits, then change the packaging and invent some hybrid setup. Next, change the materials and go nano or use light etc. instead. Even the success criteria are usually similar: energy consumption, speed or latency, size and area, cost of production, reliability and defect rate, and the integration with the existing ecosystem.
It's quite bizarre that you thought the PCM memory is a future replacement of SRAM, as the it has a switching speed of 40ns (on par with DRAM), according to the paper you cited. This is an order of magnitude slower than SRAM. The current only viable option to replace SRAM is SOT-MRAM, which TSMC is working on. Go research SOT-MRAM😁
It also involves a physical change to the medium, which means wear and limited number of writes. I believe a similar principle has been around since at least the 90s. I used to have a CD-R/W type device that used a laser to heat up spots of a special metallic medium, changing it from smooth to amorphous. Could be rewritten some number of times. I will say though, your point is probably good and valid, but could have been made more constructively.
This is true. PCM is totally useless as SRAM replacement and doesn’t have sufficient speed or rewrite resilience. Honestly, she really failed to understand its use case. It’s a great alternative to floating-gate FLASH memory, not SRAM!
The words "dynamic" and "static" are a reference to the powering method between state changes. You kind of hinted at this with the TTL logic diagram, but didn't expand. Static is faster because it doesn't have to wait for the re-fresh cycles before it can change state. Static also runs hotter and consumes more power- there are no free lunches ;-)
Not exactly. DRAM consumes power all the time, because it needs constant refresh to preserve contents. SRAM only consumes power during state change. Both consume some leakage current though, and with that, SRAM consumes more due to having more transistors per bit cell. DRAM also consumes considerable current to change state, because of its larger gate capacitance. Overall, DRAM tends to consume more power per bit but costs less and is more compact, which is why we use it for main memory and reserve SRAM for cache and internal registers.
Interesting idea, but very speculative and in need of a demonstration at scale to assess its practicality. Moreover, although a 23% decrease in area is good for an existing bottle neck, it is not revolutionary, that would need a factor of at least 10. At the current estimated level of improvement it becomes a commercial decision on whether this improvement has a fast enough pay back to justify the r&d costs to make it practical. Is anyone making the investment to commercialize this discovery? Thank you for sharing!
Not really, the silicon lattice constant is only 0.7 nanometers. We can't scale in silicon below that. Germanium has a lattice constant of about 0.5. While process nodes and technology are mostly marketing terms and there is room for improvement beyond "1 nanometer process" - we are about at the end of what we can achieve with existing semiconductor paradigms. It will be almost all architecture and material sciences by 2030. We can't get much smaller. A 20% improvement over SRAM is disruptive even if it doesn't scale any smaller. SRAM is unable to be scaled any smaller due to the physics underwriting operation. We only have a few more die shrinks left before we are up against the size of the atom. ... Again, sort of ... A 1 nanometer node doesn't necessarily mean that you can make a grid of 1 nanometer square pads separated by 1 nanometer troughs on all sides, or vice-versa. But as I mentioned, the lattice constant of silicon is 0.7 nanometers, their latest process node is 1.4 nanometers. You can't really cleave off half a crystalline arrangement without having weird things happen, the next die shrink, if it is possible, would come at 0.7 nanometers. We would be, assuming we can make the grid arrangement described, making the smallest transistors possible with silicon, using existing paradigms.... And whatever paradigm comes next would need to use atoms much more efficiently - or some other concepts entirely - to function. On the plus side, it means that in about another 10 years, we might see computers built with the idea they could last decades in their application.
@@Aim54Delta Great points! Thank you for expanding on the technological limits of the underlying physics not covered in the video. Given these fundamental limits to silicon, research efforts will move to entirely different concepts that may or may not work. Perhaps we will not see much further progress ending the decades long run of ever increasing chip performance or something new will make current silicon architectures obsolete. Fascinating field with huge commercial risk/rewards for company boards to ponder. Thank you for your comments.
Very interesting. Thanks for sharing your expertise. There is always something interesting in your videos. At least in the three or four i have seen so far.😊
Thank you for your presentation. I found it fascinating. The phase change memory, amorphous crystal back to uniform array crystal seems like the mental models used to explain demagnetization around the currie point.
I worked on micron/intels PCM, optane, for a few years. While we were making peogress on some of the problems you mentioned, the venture ultimately failed due to the economics of producing the chips as well as a lack of customers. Would be cool to see it make a comeback in the future
I thank you for your service. When intel announced that they were ending optane, I bought 6 of those PCIE drives; I caught a fire sale. Those drives are the fastest drives I have for doing some disk intensive Studio work. I wish they could've gotten the price down around $100-$200 dollars for the good stuff. I actually got 6 optanes for $45 a piece. I lucked up and bought a box.
Nice idea. Very similar to Nantero NRAM that also uses Van der Walls effect to provide resistive cells using carbon nanotubes for SSD/DRAM universal memory. I've been waiting for NRAM for 20 years, and it is only now beginning to make it's way into the data centre. Let's hope that this technology takes less time to mature.
Loved the graph you put together with the memory pyramid (access time vs where is used, with volatility information)!! P.S. Your accent also becomes more and more easy to understand!
Paul Schnitzlein taught me how to design static RAM cells. This video speaks to me. Yes the set/clear, and sense amps are all in balance. It is an analogish type circuit that can burn a lot of power when being read.
I believe that down the line we would need to use another processor architecture than the Von Neumann one that we use today (i.e. having logic and memory separated), an architecture that instead has an "on memory compute" design, or perhaps a mix of them. In the end the speed of light makes it hard to compute over longer distances (i.e. CM or even MM) specially when the frequency goes up and the data becomes even larger.
I remember hearing about the SRAM scalling issue some time before the Zen4 release, but then haven't heard anything even though I kept hearing about shinking nodes. Been curious what was coming of that. I was thinking that since it's not benefiting from the scaling, if it may have been counterproductive regarding degradation etc. I wonder if that is what is happening with the Intel 13 and 14K skus? I guess we will find out soon enough. Thanks for the update, I'm glad they are on top of it!
Thank you for this video. It's great. My two issues: (1) heat dissipation, is not addressed (over cycles there is growth of H.A.Z.), (2) One thing I heard about and remember vaguely, was an attempt at self healing logics (rather, materials + control circuitry), which is aimed at reducing the need for redundancy, in elements at the core of the chip (hottest and fastest environment), and attempts to also better the chip lifetime (cycles 'til dead). -I would be grateful if you could address both.
Great stuff. As someone who built their own desktops through computer conventions in the 90s I appreciate you bringing me up to date on where we stand now in personal computer development😊
My concern with the phase change memory is just the lifetime and reliability. Do the cells grow oxides or change chemistry over time? Can they be ruined by ripple or electrical noise at scale that hasn't been discovered yet? Etc. Love your videos!
One of the chief benefits I can see in going to optical computing is the ability to have associative addressing through polarization and muliple concurrent optical reading/writing heads for raid like processing.
This is not a solution to the SRAM problem, even the authors of the paper state "his work provides key materials and engineering insights towards the design and optimization of energy-efficient PCM, and could inspire the industry-scale adoption of nanoscale superlattice phase-change materials for low-power and high-density storage." The report states that they have a nice cell size of 45 nm, but a switching time of 40ns and endurance of 2 x 10^8 cycles (SRAM is around 10^15). So this is a possible replacement for Flash memory not SRAM. As a side note, the use of any heat based phase change storage solution on or near the CPU die would result in some very interesting performance issues as the heat output of the CPU would be impacted by the number of true values held within the cache storage and the frequency the cache is rewritten.
It has been discussed for decades that close stacking of chips has advantages of speed and size. The issue is heat generation, thus trying to reduce the total charge (electron count per bit). New memory technology is required with far smaller charge transfered per operation.
I worry about using non-volatile memory for primary or cache memory because of the security aspect. If the information remains after power is interrupted, quite a few "secrets" will be in clear text, and the determined and well equipped "bad actor" will be able to extract surprising amounts of information from a system. My industry has to issue letters of volatility with everything we produce, and for anything with NVM, the sanitization procedure usually involves removing the part with non-volatile storage and destroying it. The only exception is when it can be proven that the hardware is incapable of writing to that NVM from any component present on the assembly, even if malicious or maintenance software is loaded onto the device. This phase change memory built in the same package as the CPU logic could not be provably zeroized without some sort of non-bypassible hold up power, and that would increase the cost and size of the chip package. I think this is very promising for secondary addressable storage, but I don't see it replacing main memory in most applications.
Stacking silicon...who woulda thought ...now it makes perfect sense for chip real estate. Thank you for your brilliant assessment of the latest chip technology. You have expanded my knowledge regularly.
It should be mentioned that process node sizes like N3 or N5 nodes are density measurements and not actually a transistor size. Intel 10nm was equivalent to TSMC 7nm as they average over different area sizes and utilize different shapes and can't be compared directly or even with the size of a silicon atom which is only 0.1 nm in "size".
As always fantastic work. I am not so enthusiastic right now with the new technology an endurance of 2E8 is amazing for something like storage, but the computer will go over that in no time for the cache. Even a microprocessor that is not super scalar and runs on the ghz range will be accessing memory in the other of 10^9 per second. Clearly, that access is per cell, and not for the full memory but they need to improve that number a lot.
Thank you! Just wanted to say you have a mistake in the figure you show (e.g. 12:38) labelling the latency of flash memory as milliseconds (1/1000s) when, as you say in the audio, the latency is in microseconds (1/1000000s)
3 nm and so on is a marketing term that has no relation to any dimension of the transistors anymore. The true gate width until now is 14 nm due to asml's lithography machines limitation. The next step for the next decade is going down to 8nm (about 80 atoms wide).
Interestingly, computing is still based upon an electron pump system when the Spherical Photon Well combines logic and data storage in one system that moves at the speed of light.
What about keeping the heat down. Sure lower power required in some case but stacking should also increase the requirement for improved cooling perhaps?
Non-volatile and low-latency at the same time, coupled with scalability and hopefully cost-effectiveness in manufacturing, would be a huge technological leap. Thank you for the information.
Xilinx's (now AMD) HBM products were combining FPGAs with DRAM chiplets on a silicon interconnect substrate back in 2018. Altera released similar tech a year later.
I believe that the problem of quantum tunneling limitations to size can be addressed by temperature as well as ionic state. This implies that mechanical cooling is a requirement which is expensive and inefficient.
Thanks for the updates, really informative... I was working on OTP memory designs and this new time of glass memory is looking similar to the concept of OTP memory, may be we can see this kind of evolution in OTP memories side also.
I had thought of building memory (and the whole IC) in 3D 10 years ago. I think I even put the idea in my website years ago. One part of my idea that is not used yet is using microfluidics to cool the chips that are stacking transistors in 3D, thus restricting heat transfer. The channels could run many levels, and of course, they need fluid-tight connections (a big problem). And use optics to communicate instead of a BUS. Possibly LED or laser tech.
This sort of tech is very interesting, because depending on how it advances, it stands to change the computing landscape in one or more different ways. If Phase-Change Memory is fast enough and gets good enough density, it can replace SRAM in L3 cache. If the speed cannot get high enough, it could still find use as an L4 cache or a replacement for DRAM. If all else fails, I bet it could give Flash storage a run for its money.
OK I’m calling this out as not feasible in lots of cases. The issue is that SRAM needs to be tightly coupled into an architecture to get the performance benefit. However if a bond-out pad is required (eg chiplet etc) via Bunch Of Wires interface then there will be a delay penalty due to capacitance and transmission line issues. This means added latency and a performance hit. Might be useful for L2 cache but anything local it is of no use. SRAM at the local level is still the best solution.
what really excites me about this new PCM technology is it's analogue compatibility. i really think APUs will catch on within the next 10 years or so. and this type of RAM is perfect for that application
Yes, though theres more limitations, it's really hard to manage heat in a 3d structure. It also requires new innovative ways to do it. This is why a room temperature super conductor would be such an amazing breakthrough. You wouldn't need to worry about heat management and you could up the frequency to Thz levels while maintaining manageability even in a 3d transistor structure. Computing would be millions and billions and even trillions of times faster
So each of the 2 phases of the PCM has a different resistance, so the computer can tell 1 from 0? Can PCM memory be integrated in the same chip as the processor core? Seems like it requires a unique material to be added on a chip
PCM memory chip technology has been in R&D since the mid 2000s. Intel, StMicroelectronics and Ovonyx were in the game together in a joint development starting around 2005. Samsung was also doing research in PCM. I believe the biggest player now in Micron Technology.. And you are correct about all the advantages of PCM. I believe the two big challenges are being able program the device.into two or more distinct, well defined resistance states reliably coupled with manufacturing very small structures with precise dimensions. Nvidea is talking about PCM.
One way of attacking the Memory Wall hierarchy is to attack it from the top, use RLDRAM which has been around for >25 years but only in NPUs (network PUs) since it offers DRAM cycle rates closer to 1ns but latency of 10ns or 8 clocks. Since it is highly banked, 16-64 banks working concurrently allows for 8 memory accesses every 8 clocks so throughput is 2 orders better than conventional DRAM. Of course in single thread use, not much benefit and to keep as many threads in flight requires that thread selects pseudo randomly across the banks and not hit on the same bank successivly.This could be used as an extra layer between normal DRAM on slow DIMM packages and the first SRAM cache level. This RLDRAM layer is where it would be used in CAM modules or soldered. We are substituting The Memory Wall for a Thread Wall here. But we already are used to having dozen threads these days. The RLDRAM model could be applied one level lower down in an RLSRAM version which would be perhaps several times faster but allow bank cycles and latency near 1-2ns but still 8 clocks and 16 banks.
@Anastasi - you might want to re-post this video taking Intel Optane memory into account. It's a non-volatile PCM memory that's been out for years, and even used as DRAM. As another comment mentioned, it failed due to the expensive manufacturing of the chips and the market simply wasn't there mostly due to fierce competition from flash memory.
optane's real problem was it being place in 2 places where it didn't belong, one was a flash competitor which placed it in a much too slow interface, another was in DIMM competing with much faster Dram chips, if we make a dedicated space for it optane could really bring some benefit but we need to do it the right way.
A nonvolatile cache memory creates exciting new ways that processor microcode that can be infected with impossible to trace privacy stealing back doors.
Although I do not comprehend all the things you mentioned, what I do understand I find very fascinating. Yours and videos of others help me to decide on what companies and technologies in which to invest (= gambling) at the Wall Street Casino. Investing in stock is like playing Black Jack. The more you know such as via "card counting", the better your chances of winning. For me, your advice is akin to card counting when it comes to gambling on stock purchases. Thanks for your insight in this realm. BTW, my 1st computer was an Atari 800XL which I purchased in 1985. I also wrote code in Atari Basic and in HiSoft Basic. Ten years later, I used the program I wrote to analyze the data for my Master's degree in Human Nutrition. With the Windows computers, writing code now has become too complicated for me, so I have given up on that endeavor.
You can put it another way. Anastasi did her best in NOT acknowledging that it was an advertisement. It's my personal opinion that it is unprofessional and misleading to viewers to not acknowledge such fact in the video. There isn't a single ad tag in the video description...
Great video - thank you Anastasi :-) I think if we stack much more memory as 3rd level cache chiplets on top of CPUs we may reach the size of gigabyte 3rd level cache. And this would eliminate the external DIMMs on the mainboard which makes future Notebooks and PC again cheaper and reduces not just the complexity of the mainboard but also of the operating system, drivers and firmware because data can be loaded directly via fast PCIe lanes connected SSDs to 3rd level cache.
Yeah memory has reached a wall. Gee finally a youtuber who knows wtf its talking about lol. Great channel and great video. V-cache is still a very tiny amount of cache. If we could have gigs of 3D V cache directly on the cpu/gpu thatd be awesome... but we cant do it. Imagine 64 gigs of eSRAM directly on the cpu/gpu die, going at terabytes per second, it would be a huge boost compared to the 60 gigs per second you get with top of the line DDR5 and the sub 1ns response time...
Amazing content! Very interesting and intriguing as always. I was surprised to see how small the logic section of the chip was relative to the sram, it makes sense that it's stuck at 3nm because of the structure is 3 transistors wide.
14:05 Anastasi: 0.16 micro m² 🤔 Subtitles: 0.016 micro m²🤓 I think you you should pronounce every number after decimals one by one rather than calling them at once
Great content! Please stop the zoom in/out effect when cutting your video. There is so much of it I get nauseous watching. Otherwise, you do an excellent job explaining this interesting topic.
PCM durability? Write cycles lifetime? That fusing/recristalizing events look like whould degrade the structure making it less efficient with time. Then it would substitute storage memory with great success, but woulnd't be able to be applied as SRAM / cache.
