Thank you. This tuturial is excellent. I would happily pay over $2400 (US) for Vipin Kizhepatt's course if he ever offered one! I mentioned $2400 because that's how much Xilinx wants for their training.
You have to pay more for university course which is even worse than Xilinx training, not to mention Vipin Kizhepatt. The only disadvantage is that the course is out-of-date and terrible accent (the same disadvantages exist in university course).
@@hengzhou4566 how is it out of date the zynq board he's working on is like 10 years old and the videos only 3-4 years old, coming to the accent is it really that bad to understand?
A great tutorial! Thank you for your effort. I am very sad to see that you have gone away 1 years ago. I hope you will come back again. I would be very pleased if you can write if you are planning to come back and upload any other videos in the future. Thank you.
The work you have done by uploading the lectures in a great thing and helps the students to understand the Vivado well !! Could you please tell your system configuration where it is very fast in simulating ? Thank You for all you effort sir It means a lot to share such a knowledge
The name of the signals change slightly after synthesis, sometimes you can not find the exact node that you are looking for. So this method has limits.
Hello ,Sir I am working on a project related to FFT and require to give 32 bit inputs and observe 32 bit outputs.Could you please help me with pin assignments.
Excellent tutorial sir. Thanks for taking so much efforts. Can you please make such video on APB protocol. If it's already there can you please share the link.
ILA is also implemented using FPGA logic. So as the number of signals and number of samples increases, the possibility of timing violation also increases.
