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J K Flip flop ( English) 

Engineering Physics, Digital ,Architecture
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Lecture by - Dr. M. Balasubramanian
JK flip Flop is designed using SR Flip Flop.
HOW the forbidden condition of SR Flip flop resolved is explained. Toggle condition is discussed.
Race around condition is also explained.

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16 сен 2024

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Комментарии : 43   
@Phantom-fi8sc
@Phantom-fi8sc 4 года назад
truly appreciate your teaching sir, regards from sri lanka
@physicsanddigitalelectroni2151
@physicsanddigitalelectroni2151 4 года назад
Thank you 😀
@RAKESHKUMAR-fc5lx
@RAKESHKUMAR-fc5lx 4 года назад
You lectures are awesome... 🏅
@timoskar1574
@timoskar1574 6 лет назад
really nice explained - Thank You, sir! cheers from Germany
@vijayadurgak470
@vijayadurgak470 4 года назад
Thank you so much sir.. your videos are so helpful to prepare for exams.. and getting the topics so simply to understand..
@Vayanovic
@Vayanovic 5 лет назад
This is fantastic. Old school but brilliant, MANY THANKS.
@sniranjanaece
@sniranjanaece 6 лет назад
Hayo really tanx a lot sir... It's more easy to understand.... Once again tanx...
@learningexpress6224
@learningexpress6224 5 лет назад
Thanks a lot
@JohnSamuelM-nt3vx
@JohnSamuelM-nt3vx 7 лет назад
awesome teaching sir....
@siddagondkabadagi274
@siddagondkabadagi274 3 года назад
nice explaination
@godlove325
@godlove325 4 года назад
Excellent class
@EDUTAINMENT56
@EDUTAINMENT56 5 лет назад
Superbly explained sir 👍👍👍👍👍💐💐💐
@narshimahreddy6105
@narshimahreddy6105 6 лет назад
Nice sir ..... Good job...👌👌
@learningexpress6224
@learningexpress6224 5 лет назад
Great Work
@mariyafrancis6207
@mariyafrancis6207 6 лет назад
nice class very easy to understand
@ev.sachin
@ev.sachin 7 лет назад
Nice sir...Good job..🙏👌
@11shaddy
@11shaddy 7 лет назад
Very Nice Sir, We are easy to understand you Way and I Need to learn Timing diagram in depth knowledge, could please post the same. Thanks in advance
@debjitkarar5066
@debjitkarar5066 7 лет назад
sir if u would have taken A as a select line then there would be no such problem with C
@varunverma6353
@varunverma6353 7 лет назад
nice & easy to understand
@sumansunil9630
@sumansunil9630 6 лет назад
It's really helped me a lot sir but need to know more about it sir.......
@learningexpress6224
@learningexpress6224 5 лет назад
Great Work
@ramyasaidintakurthi3180
@ramyasaidintakurthi3180 4 года назад
Thank you so much sir very great and easy teaching 🙏
@nurudeenadewale4213
@nurudeenadewale4213 6 лет назад
wow....i love your lectures...thanks!
@ZORO-xj8vz
@ZORO-xj8vz 4 года назад
Thank you sir......
@TechSpeedup
@TechSpeedup 6 лет назад
Sir , Make lecture of T -flip flop also with exication table,characterstic equation and truth table. Thank you.
@learningexpress6224
@learningexpress6224 5 лет назад
Superb
@kldrhmn8324
@kldrhmn8324 6 лет назад
great explanation
@learningexpress6224
@learningexpress6224 5 лет назад
Great
@sujitsharma5158
@sujitsharma5158 6 лет назад
too good....👍👍
@learningexpress6224
@learningexpress6224 5 лет назад
Too Good
@SureshRaina-nz9uq
@SureshRaina-nz9uq 7 лет назад
Thank u sir
@alajlan2012
@alajlan2012 6 лет назад
🌹 you deserve the Phd , regards from Saudi Arabia
@learningexpress6224
@learningexpress6224 5 лет назад
Hats Off Sir
@akshithtalks179
@akshithtalks179 6 лет назад
If both j&k is zero than?
@learningexpress6224
@learningexpress6224 5 лет назад
If both are zero ?
@preetichaubey9211
@preetichaubey9211 6 лет назад
Thank you sir😊
@westonmpangala2289
@westonmpangala2289 7 лет назад
ilike it, from tanzania
@physicsanddigitalelectroni2151
Thank you very much
@sandeepkadiyam8004
@sandeepkadiyam8004 7 лет назад
which gate is used for input j&k And(OR)NAND
@bhavya5508
@bhavya5508 7 лет назад
Sandeep Kadiyam nand
@ninag2489
@ninag2489 6 лет назад
If SR ff is made of Nand gate then isn't output is supposed to be 0 when S=1 and R=0
@sumanjyoti6063
@sumanjyoti6063 5 лет назад
In the truth table for SR flipflop, the third value in Q column must be 0 bcoz previous state is 0, how can it be 1 again?
@sumelbhuiyan7087
@sumelbhuiyan7087 4 года назад
N
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