JFET Biasing: Fixed Bias Configuration Explained (with Solved Examples)

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In this video, the Fixed- Bias Configuration of JFET is explained with solved examples.
By watching this video, you will learn the following topics:
0:31 What is Biasing and Different Regions of Operation of JFET
4:40 JFET Fixed Bias Configuration (Circuit Analysis)
8:51 Example 1
13:35 Example 2
17:33 Example 3 (p-channel JFET Example)
What is Biasing?
Biasing is the process of establishing the proper operating voltage and current in the circuit, such that the JFET can be operated in the specific region (Active, linear or cut-off) for a particular application.
In this video, the fixed bias configuration of the JFET and its circuit analysis has been explained. And three different examples have been solved for the fixed bias configuration.
The other videos related to Field Effect Transistor (FET):
1. What is Field Effect Transistor (FET)?
• What is Field Effect T...
2. Construction and Working JFET
• JFET: Construction and...
3. Transfer Characteristics of JFET
• JFET Transfer Characte...
This video will be helpful to all the students of science and engineering in understanding the Fixed Bias Configuration of the JFET.
#JFETBiasing
#FixedBiasConfiguration
#JFETSolvedExamples
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Опубликовано:

8 фев 2019

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Комментарии : 52

@ALLABOUTELECTRONICS 5 лет назад

The timestamps for the different topics covered in the video: 0:31 What is Biasing and Different Regions of Operation of JFET 4:40 JFET Fixed Bias Configuration (Circuit Analysis) 8:51 Example 1 13:35 Example 2 17:33 Example 3 (p-channel JFET Example)

@mayukhmalidas 3 года назад

Tomorrow is my analog exams !! And here we are finishing JFET biasing . Thanks a lot for the vids !

@kalyanib3017 5 лет назад

Thanks for the video ! They make concepts crystal clear !

@poojashah6183 5 лет назад

Sooo true 👍

@shreyash942 4 года назад

Excellent stuff ! Just keep it up with the videos.... Thank you.

@YdvSyAero 2 года назад

dear sir , it is very difficult to write notes along with your lecture . If you provide notes in pdf form then it will be awesome

@aarya7771 5 лет назад

Thank you so much it become so much easier

@tyakashigwedha4057 Год назад

Sir i really thank your effort for this video you really made it easy to me you know what you are doing 😇😇

@sbonelobonengcongo2262 4 года назад

thanks a lot sir you are the best

@sayanpradhan1236 4 года назад

Thank you sir 🔥

@radha_preymi 3 года назад

Great video sir 👍👍👌💚

@doitbyyourselff 3 года назад

Best Explanation

@mayurshah9131 5 лет назад

Superb!!!

@ashutoshmishra6872 5 лет назад

Thank u Sir...

@mayurshah9131 5 лет назад

Very nice

@s.k.g5544 3 года назад

Awesome 👍

@mertdeffendermaster3613 Год назад

thank u from turkey sir

@masbro1901 3 года назад

9:42 this Vgs = -Vgg is from KVL right? Vgs + Vgg = 0. i thought its from reverse polarity Vgg because terminal G has positif polarity but the bias DC its from negative source. so Vgs = -Vgg . its not from that. but then G terminal has positive polarity and DC bias voltage Vgg has negative, what happen when that happen? + meet - does it still work? forgive my newbie.. please explain...

@surbhikakumari7581 4 года назад

Sir can you please tell the exact condition for n channel and P channel JFET to operate in Saturation region? It has become a bit confusing for me.

@ALLABOUTELECTRONICS 4 года назад

I have already mentioned the condition at 2:33 in the video. The only thing you need to keep in mind is for p-channel JFET, Vds is negative and VGs is positive. For, n-channel JFET, Vds is positive and Vgs is negative. I hope it will clear your doubt.

@rajitdas558 4 года назад

@@ALLABOUTELECTRONICS for n-channel is the vp positive or negative

@poojashah6183 5 лет назад

👍👍

@LostInLeiden 3 года назад

At 11:13 are IDSS and VP properties of the FET itself so you can look them up in the datasheet?

@TechnicallyExplained 3 года назад

yes idss and vp are constants and are given on specification sheet

@technovert1614 3 года назад

can you do videos based on JFET amplifier

@ALLABOUTELECTRONICS 3 года назад

I will also cover it along with MOS amplifier.

@mixedvideos2800 2 года назад

where to find the value of VGSQ?

@aswathi8872 Год назад

gonna crack the internal.

@masbro1901 3 года назад

5:17 forgive my newbie, so there's two analysis can we analyze from a circuit, AC dan DC input. but you said its used as amplification AC signal, so the output is AC signal too which has been amplified, right? then why and how come you interested in DC analysis of the circuit? please enlight me.. and 2nd Question is at 5:47, if high impedance why Ig approximately equal to 0 ? what is explanation behind that..many thanks..

@ALLABOUTELECTRONICS 3 года назад

To use JFET as an amplifier, it needs to be DC biased properly, so that the AC signal can be amplified properly. Proper DC biasing is essential for AC signal amplification (without distortion). Regarding your second question, the gate terminal provides insulation (high resistance) at low frequencies. Therefore, the current going into the gate terminal is negligible and can be assumed as zero. I hope it will clear your doubts.

@black-sci 3 года назад

Do you use *boylestad and nashelsky electronic devices and circuits*

@TechnicallyExplained 3 года назад

I use boylestad

@shoaibsaqi8568 3 года назад

9:25 Sir when the input resistance is very high it needs to be considered as an open circuit but it has been said in video short circuit and all voltage should dropped in one Mega ohm. I get confused please make it clear

@ALLABOUTELECTRONICS 3 года назад

The thing is, since Ig is approximately equal to zero, there won't be any voltage drop across 1 MΩ resistor. And since, there is no voltage drop across it, it will not have any impact on the cirucit operation as far as DC analysis is concerend. In short, -2V will appear between the gate ans source terminal. And Vgs = -2V. I hope it will clear your doubt.

@LemuelJefferson Год назад

@@ALLABOUTELECTRONICS i dont see it right

@noweare1 5 лет назад

@10:41 Vds > Vgs - Vp I don't understand . If Vgs=0 then Vds must be greater than -Vp why the negative since Saturation when Vgs =0 is when Vds > Vp not negative Vp ? Thank you.

@ALLABOUTELECTRONICS 5 лет назад

Hi, please look once again at 1:53, for n-channel JFET, the condition for saturation is Vds >= Vgs- Vp. If Vgs is zero then Vds has to be greater than -Vp. The thing is for n-channel JFET, Vds is positive and Vp is negative. That is why that negative sign comes. (So, that equation is correct in mathematical terms) I hope it will clear your doubt. If you still have any doubt then do let me know here.

@noweare1 5 лет назад

@@ALLABOUTELECTRONICS Your comment above that Vp is negavitve is not correct, it's positive, see your transfer characteristic. You are saying Vp but I think you mean Vgs at cutoff. For an N channel JFET Vds is positive, Vp is also positive, Vp is the value of Vds when Ids no longer increases. At cutoff Vgs = -Vp

@shakiraakbar6072 4 года назад

Sir@10.02. Vgg=-2v and wkt Vgs=-Vgg hence Vgs=-(-2)v=2v. Am I correct or not ??🧐🤔

@TechnicallyExplained 3 года назад

no vgs=-2V

@aliyarc.a150 3 года назад

Can you please tell me why we're doing DC analysis??

@ALLABOUTELECTRONICS 3 года назад

To use any FET( JFET or MOSFET) as an amplifier it needs to be DC biased properly. So, that it can amplify the AC input signal. Whether signal will get amplifier properly or not and whether we will get proper voltage swing or not depends on biasing. That's why DC analysis is very important aspect for any BJT, MOSFET or JFET amplifier. I hope it will clear your doubt.

@TechnicallyExplained 3 года назад

To find the Q-point i.e operating point

@HMHuon9 Год назад

Sir, why do we need R_G when no current goes to the Gate terminal?

@079_zubairfarooq9 Год назад

There is no current flowing in gate but there is a voltage at gate terminal : +ve or -ve depending upon type of transistor 'p or n' this voltage at gate terminal is necessary for creating a path(channel) for current flow between drain and source terminal . If the voltage applied at gate terminal is +ve electrons are pulled towards it due to electric field as a result these electrons are accumulated at insulated layer submerged between gate and P type thereby creating a channel for current flow.

@HoangNguyen-wx6ii Год назад

@@079_zubairfarooq9 It's not for DC bias, if you learn about AC analyst you will understand why.

@rukshanfdoable 3 года назад

I confuse in Value of Vp minus or plus.please guide me

@ALLABOUTELECTRONICS 3 года назад

For n-channel JFET pinch-off voltage Vp is negative. While for p-type JFET it is positive.

@mohankrishna3858 10 месяцев назад

Why are we using capistors in the circuit @ALLABOUTELECTRONICS

@ALLABOUTELECTRONICS 10 месяцев назад

They are used to couple the AC input signal to the amplifier circuit. DC voltage ensures the proper biasing to the circuit. And on top of the biasing when small input signal is applied then circuit will amplify that input signal. To couple the small AC input signal to the circuit, capacitors are used on the input side. Similarly on the output side, to block the DC voltage and to just pass the amplified AC signal, capacitor is used.

@mohankrishna3858 10 месяцев назад

@@ALLABOUTELECTRONICS doesn't the input capasitor block the input DC and prevent the circuit to be able to biased

@ALLABOUTELECTRONICS 10 месяцев назад

If you closely observe, the circuit is already biased. Of course, the capacitor will block the DC. That means if you connect the multiple stages of the amplifier then DC voltage of one circuit will not interfere with next stage. And only AC voltage will get coupled. But the capacitor will not block the biasing of that specific stage. The biasing is provided through external sources and resistors. I hope, it will clear your doubt.