Thank you so much, you are a lifesaver. My professor decide to do last minute exam about this JK flip flop timing and I stumble upon this vid and it helped me so much.
@Joe Haas .. I"M I the only one who noticed the mistake with the second example? or please correct me if i"m wrong. With the active low, our output will be activated when the input is "0" . But he went on seting and resenting, using the active high format. Please correct me if i"m wrong, but i"m pretty sure he made a mistake there.
Thanks so much for the comment. I am pretty sure that I did the second example correct. With the active low, I am setting or resetting when the clock goes edge goes from 1 to 0.
Ok thank you so much! Just to clarify sorry for so many questions I just really want to make sure I’m on the right track xD If the synchronous reset is active on the rising edge of the clock does the Q pin go immediately low?
wtf dude u fucking serious i am literally like an idiot wasting 8 hour studying on these still cant understand, and you use 6 minutes to let me understand, fucking god lifesavier, i wish you can acheieve everything u want to in ur life, love from malaysia
Clk yazan clock yerinin önünde yuvarlak top varsa negatif edge demek aşağıya doğru olan 1 den 0 a gidenler. Ama yoksa top falan yukarı doğru giden 0 dan bire bakıyorsun
@Acss47 bahsedeyim ama pek bi bilgim yok açıkçası eğer üniversitede ve benim gibi digital dersinde görüyorsan bunları zaten senkron olarak görüyosun hep asenkron bize göstermediler maalesef