Thank you for putting up the recommended readings they have helped a ton. Also thank you for putting these lectures on the internet. They have aged well.
Does FPGA have dataflow execution? It seems that it just emulates electric circtuits and logic gates. I also feel that it is natural to think in dataflow model when I program in HDL.
I want to ask a question. I'm an undergraduate in ECE department. Here, professor shows a lot of papers throughout the classes and how does it possible to review the class study, do the homeworks, projects and also READ the papers(several for must read papers but pretty much a lot for recommended papers)? In my country one semester is like four month and we attend like 5 major courses in one semester. Does this situation same for you guys in america, too? Great lecture btw.
at 1:20:00 why do we need a barrier synch? why can't we start merging as soon as the next(/first) thread completes execution? was it just a way to solve the problem that the instructor was discussing?
@@nebimertaydin3187 I don't believe it's the same performance. Assuming you can detect early finishing threads, you can bypass the load imbalance issue mentioned at 1:23:12.
The lecture is good but the camera work is terrible. If you don't show the screen, I may as well be a blind person taking the course. I gave up after this lecture.
