LMARV-1 reboot part 6: About CSRs and interrupts 

Little psychology tip: when giving people a set of alternatives, always give them the choice that you want to encourage them to pick as the last option. If they are indifferent, and don't care which one, they will tend to pick the last one, because it is easiest to remember. Should be more like, "upvote if you thought it was useful", and just omit the not up-voting, the "if" covers it!

Im already feeling the anxiety of this becoming a huge project 😋

If ECALL, context switches, etc. seem to be too problematic, you can opt for not supporting interrupts in V1 of your hardware or only support it in a limited fashion (Machine level external interrupt routine for IO), especially if you have a microcontroler-like machinelevel-only hardware. V2 of your hardware (or nMigen simulation) then can add more and more. It is easy to lose oneself in the vast space of Interrupts, context switches, and the dozens and dozens of CSRs Risc-v can support. But since right now you are also in control of the software that will run on your hardware, you can limit the support as far as needed to have a minimum-viable-hardware, and add more later. Helps preventing frustration :)

Thank you

17:10 I think that ecall from machine mode in that table is Interrupt=0, ExceptionCode=11 and ebreak is Interrupt=0, ExceptionCode=3.

ECALL vs INT: x86 has a similar situation with the SYSCALL and INT 80h semantic. SYSCALL on x86 is newer/faster, vs the old method of setting up registers and then calling INT 80h (which is simply a random convention in software like MS-DOS or old windows, etc). RISC-V maps ECALL to various interrupts, depending on wether the ECALL happened in User/Supervisor/Machine mode. This is the way how RISC-V performs kernel calls (setup registers in user mode, then call ECALL, which is handled by a handler running in Supervisor / machine mode). If you only want to run privileged machine level code like in a microcontroller without an operating system, ECALL would always hit INT 0/11. You can also skip calling ECALL in such a case, since you'd anyway just call whatever code you want. RISC-V also supports interrupt handling, and software can setup and trigger interrupts. Google For the SiFive Interrupt Cookbook: sifive.cdn.prismic.io/sifive/0d163928-2128-42be-a75a-464df65e04e0_sifive-interrupt-cookbook.pdf SiFive is the company that is driving RISC-V software and hardware development the most prominent, and their interrupt overview is quite nice.

I am concerned about conditional jump. PC+4 at interrupt return might not work. But I didn't read the RISCV documentation about it.

Amazing. As a matter of curiosity, did the previous ttl tangible version were built using bit slices? Let’s say amd 4bit or whatever. I remember some Apollo workstation emulating a 68k10 Instruction Set out of amd bit slices.