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Magic of K-Map | 30 Days of Verilog Coding | Day 24 

whyRD
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21 окт 2024

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Комментарии : 7   
@shamsherlykhanpathan7489
@shamsherlykhanpathan7489 17 дней назад
module top_module ( input [1:0] A, input [1:0] B, output z ); always @(*) begin case({A,B}) 4'b0000: z=1; 4'b0101: z=1; 4'b1010: z=1; 4'b1111: z=1; default : z=0; endcase end endmodule thank you brother for making me use my brain to use concatenation here..... i found the above one to be the best alternative as we dont have grouping of kmps.
@PilatesinSacramento
@PilatesinSacramento Год назад
Fantastic! You've gotten me pretty much caught up on K-Maps. Now, I'll just crack open the ol' Digital Logic text book and a quick review and I'll be good! Thank you, again!
@whyRD
@whyRD Год назад
You’re welcome ☺️
@nissanbiswas8432
@nissanbiswas8432 Год назад
Another perfect lecture.
@sabrinarabbani7848
@sabrinarabbani7848 3 месяца назад
@whyRD: Hello, enjoying your lectures so far. I had a question on this problem though. So instead of using k-map can we use an "if" loop/"if" procedural block to write the code? I used "if" block and got a "success".
@abid12121
@abid12121 4 месяца назад
Hi @whyRD, we have output at 1010 then in k-map, why would you put 1 @9 ? i think it should be at 10
@ksscience
@ksscience Год назад
Sir English and Hindi language bole please
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