Timestamps for the different topics covered in the video: 0:00 Introduction 0:37 The need for Biasing in MOSFET Amplifier 3:56 Fixed Bias Configuration 9:56 Voltage Divider Bias 14:47 Drain Feedback Bias 16:21 Constant Current Biasing
0:25 why we need to bias the MOSFET 0:39 we want to use the MOSFET as an amplifier 我們要把 MOSFET當成一個放大器 0:42 that means whenever we apply a small input to hte MOSFET ,then we should get the amplifier output signal 照理講，這個用MOSFET做成的放大器，如果輸入一個小訊號，應該要給我們一個把該訊號放大之後的訊號 0:49 - 0:59 But if we just apply a small input signal between the gate and the source then we directly can not get the amplifier output.And that is because of the MOSFET characteristics . 但實際上如果我們給MOSFET一個小訊號，他不會給我們一個放大的訊號，這點我們可以從MOSFET的I-V特性圖 看出來 1:01 - 1:09 if you see the transfer characteristic of the enhancement type MOSFET,then it starts conducting when the voltage VGS is greater than the threshold voltage 1:10-1:19 That means whenever we directly apply a small input signal of a few mV between the gate and the source terminal then the MOSFET will not get turned ON.這意味著當我們直接給一個大約只有幾 mV 的電壓給 gate 和 source , then MOSFET就不會打開 1:19-1:24 That means there has to have some DC biasing voltage which is greater than the threshold.這意味著 必須用一些 大於門檻電壓的 直流偏壓電壓 （意思就是說加一個大於門檻電壓的直流偏壓電壓來解決MOSFET無法啟動的問題） 1:48 - 1:56 whenever we want to use the MOSFET as an amplifier, then it needs to be operated in the saturation region 1:56 because in this saturation region the drain current remain constant 2:09-2:15 That means by controlling the voltage VGS ,the drain current can be controlled 3:48 - 3:55 Now,the easiest way to bias this MOSFET is by applying a fixed voltage between this gate and the source terminal. 3:57 - 4:05 so,here,since this gate current IG is approximately equal to zero(因為 G terminal 絕緣) 所以在Rg上面幾乎沒有壓降 4:05 - 4:11 that means in this case,the voltage VGS is equal to VGG 4:11 - 4:17 and on top of it , a small input signal can be applied through this coupling capacitor. 4:17 - 4:22 but for the dc analysis ,this coupling capacitor will act as an open circuit.(電容對直流來說是斷路，電容對交流來說是短路) 注意：open circuit是斷路 6:43 - 6:55 in the graph ,the yellow line means load line.That means whenever this voltage VDS is equal to zero,then the drain current ID is equal to VDD/RD 6:56 - 7:02 And whenever this ID is equal to zero ,then the voltage VDS is equal to VDD.（由圖中看出來的） 8:33 - 8:42 now,although this fixed bias is a very simple biasing technique ,it is not a good approach to bias the MOSFET. 8:42-8:50 the reason is ,in this configuration ,the biasing poit is very susceptible to the change in the temperature as well as the other MOSFET parameters.因為在這種組態，biasing point 非常容易受到溫度影響，因為溫度會影響 MOSFET的常數 8:51 - 9:00 For example,this mobility and the threshold voltage are temperature dependent. (意思就是溫度一旦變化，參數都會變化，所以ID也會跟著變化) 9:46-9:51 That means in terms of the biasing stability ,this fixed bias is not an ideal biasing technique. 9:51- 9:56 and this biasing stability can be improved using the voltage diveider bias. 10:03 - 10:16 because the IG is approximately equal to 0 ,so the current flow through the R1 and R2. That means using these two resistors ,we can decide the gate voltage.(用分壓定理) 10:24 - 10:34 so here ,the ac input signal is applied using the coupling capacitor.but for the dc analysis ,these coupling capacitors will act as an open circuit. 10:35 - 10:46 VG is equal to [R2/(R2+R1)]*VDD（分壓定理） 10:46 - 10:54 and once we know this gate voltage ,then by applying the KVL（克希荷夫定律） in this loop ,we can find the relationship between VG and the drain current. 11:03 - 11:14 VG-VGS-ID*RS=0(by KVL) 12:04-12:20 VDD-ID*RD-VDS-ID*RS=0(by KVL)
Another video that didn't help me understand practically. It would be great if you could make a practical video explaining mosfets as switch, as a resistor and as an amplifier.
At time stamp 16:08 I think the simplified symbol for the enhanced P channel should show the arrow on the lower (source) and point inwards to show current flow direction. Is your diagram correct?
Dear sir I will write gate EC this year and I want to know which branch in MTech is better in terms of placement and also which college is best for that branch?
It is Ok. Usually, it is not as good as VLSI. But it may change with year to year, and depends on the companies which are participating in the placement.
@@ALLABOUTELECTRONICS thankyou so much sir for all this information. One last question sir do branch matters or college matters? For example lower branch in IIT D(old IITs ) or VLSI in NIT TRICHY (south nit's)Which option I should go for??
How do I decide or find the biasing current for correctly reaching saturation region. If you can show through a datasheet it will be great for instance Mrf300 ldmos
Thanks but I got confused from minute 13:00, the formula Vgs = Vg - Id * Rs, if Vgs =0 then transistor is OFF, then no current is flowing at Id, therefore how is possible that Id = Vg / Rs. Thanks again
The yellow line, Vgs = Vg - Id*Rs is load line. And does not represent the actual current through the device. The intersection of the load line with the transfer curve will give you the actual current and voltage of the device.
@@ALLABOUTELECTRONICS First of all, thank you for your interest. I found only this video on the list "ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-vBvLu3euc2Q.html" , but it's not exactly what I want. I want to prove Zi, Zo and Av equations with DC and AC analysis for Voltage-Divider Bias Enhancement Type MOSFET.
D-mosfet has both depletion mode and enhancement mode but it is called depletion type mosfet...for n-channel depletion type mosfet, when vgs>0V, we have enhancement mode in D-mosfet
