Op Amp Amplifier with Electronic Gain Control: How does it work? 

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Thanks for sharing. I would put a cap between R2 and Drain of the T2 and put high impedance say 100K from drain of T2 to 1V and the same thing for T1( that is high impedance say 100K from drain of T1 to 1V). This way you ensure that the two transistors are matched at DC, to get your equivalent resistor. The AC signal gets coupled through the cap.

I learned something new!!! Thx

Very interesting 👍

The falstad simulator shows difference in behavior between jfet and mosfet.

I very much enjoy these analyses of yours but invariably questions pop up in my mind: what would happen if I wanted to assemble the real circuit, using concrete hardware, say a particular op-amp or a particular JFET? What parameters of the devices I should take into account, given a particular application, or what additional devices I would have to use to make this practical implementation work. It would be very interesting to have this discussion using an example of this or any other circuit you analyzed before. Anyway, thank you for this one; as always very interesting and educational.

I'm probably missing something obvious. Why not use a single linear mosfet (generally used for its linear VI characteristics in instruments), use a control voltage to drive it directly and set the variable resistance in a single stage configuration ?

Did you solve the equation for the control function where the classic MOS/JFET function in linear region is used? I came across a similar problem where i want to adjust the MOS driving voltage for the switches in a R2R DAC so that they are a precise fraction of a linear resistor. One solution to this is to have a Vds voltage drop for the same unit current drop to the fraction resistor electronic regulated. The practical problem is that if the fractional voltage get into the region of the offset voltages of the regulator this get inprecise. I guess that the control function is nonlinear in both, the control voltage and the signal voltage. The nonlinearity of your problem sound similar to the problem i had; I need to operate the regulation circuit far from the operating point inside the R2D+MOS application to avoid strong mismatches because of regulator offset voltages. I found a solution by using a "third" MOS operating in saturation defining with the same Vgs the unit current. This current is different over PVT to the R2R+MOS but the solution is to force the Ids via a current mirror bank to the upscaled fraction resistor and the "rds" measurement resistor at the same time. Sadly the patent do not contain the math derivation: patentimages.storage.googleapis.com/61/52/50/6ec461abe5e4db/DE102007055104A1.pdf A good exercise would to apply the patent idea to a more linear control circuit with the basic operation like yours.

Hi, I think could be interesting a single power supply version of this circuit. I would be rather interested, at least.

OK, from a first look - JFET resistance is equal to Vref / (-Vcontrol/R1). So voltage gain of second opamp is R2/RJfet + 1. This is because inverting input of opamp 1 is at virtual ground, so the opamp output will set Vgs of both JFETs in a way so that JFET1 will source current equal to Vcontrol/R1, as JFET2 is matched it will have identical resistance. Wonder if I'm right 😂

Thanks a lot for your videos my friend, they are extremely well explained. In 4:07 why -3.5v??

Is there a way to control the gain using a positive Vc between 0-5V, like an analog out from a microcontroller?

Interesting ideas there, always a pleausre seeing different ideas especially around manipulating key paramters to mimic different use cases. I feel my question is trivial but i will ask it anyhow. I imagine the same can be made using a BJT or a mosfet? JFET are a little bit less ubiquitous than their relatives.

Very interesting! Never saw this topology before. Two questions: Is there any control voltage feedthru? Or it's free from it? And, is the Vref voltage be arbitrary? Or one have to find the correct one?

Why the output of first opamp connected to gates of the FET?? The FET already has voltage on the gate from the current Id

Is it possible to replace JFET->MOSFET somehow? What is THD of the circuit we could get?

Nice example of an Op-Amp + FET based Variable gain amplifier, but you completely lost yourself in the explanation of the first half of the circuit. The idea being very simple, that is, to linearize the Vgs to Rds (on the first half), by inserting the 1st FET in the feedback loop of the 1st Op-Amp and, by doing so, generating a control voltage to the 2nd FET, that is compensated for the non-linear Vgs to Rds relationship of the FET, thus linearizing the -Vc to Gain relationship, one such a thing that would not be the case if one would apply -Vc to directly control the Rds of the 2nd FET.