Output or Drain Characteristics of JFET 

As we make Vgs more positive the two deplition regions width will decrases and no opposition to the charges, then the resistance is almost equal to 0,so the transister become a short circuit.

As we make Vgs more positive then drain current will be permanent zero because Vgs will consume all electron from source terminal.

If we attempt to apply Vgs>0 (in case of a n-channel JFET) ,the gate-channel junction becomes forward biased.As a result,the gate will no longer control the channel.

sir thxxalot. tomorrow is my presentation on this topic, so yeahhh you help me understand better. May u live well.

Very clear concept.Nice tutorial.This helped me much.

Actually, we can make Vgs +ve. Well, in that case, to get the same amount of the increase in the depletion region, we will need more higher Vdd or Vds.

its my humble request when anyone has given right answer in comment u can pinned this comment that can b helpful for persons which have any doubt.

These videos are awesome..... You always save the day bro......THANKS ALOT......... 😘😘😘😘

Tqsm sir... U r doing a great job...god blessings always with u sir...

thank you sir ,,this is so excellent ,,keep up the good work

Amazing videos on JFET. Thanks a lot sir..

Good video sir....Your explanation is very good and simple understand language..I like your video.

If we apply VGS>>0 then it becomes forward bias . We know that in forward bias the current flows easily with out any depletion layer. So if we give +ve VGS no depletion layer occurs !! If my answer is wrong pls say the correct answer

nice presentation...covered each topics meticulously... pls cover rest electronic subjects as well :)

Tq so much for such neat & clear explanation sir .....and my answer is when we increase Vgs To positive there is no increase of depletion region hence the current increases

if we go on making Vgs +ve (in case of n-channel JFET) then "pinch of" will not take place because for n-channel JFET required condition for Pinch Of is Vgs should become more and more negative.....and by doing so we will never reach "Idss"(saturation current).

Thankyou sir , for such a wonderful explanation.

Thanks again for the lecture.

Excellent presentation! Thank you. One of the major lessons is that the pinch-off voltage is not a constant but instead depends on Vds. Interesting that the manufacturers only provide one value for pinch-off voltage.

Thank u sir. You are a great

When vgs >0, forward bias will exit,so that depletion layer decreases n channel increases and the current will increase linearly . SO THE GRAPH IS LINEAR STRAIGHT LINE.

It would be really helpful if you could upload MOSFET videos as well

for n channel jfet if vgs is made positive then that will lead to forward bias condition as a result current id will increase drastically lead to the damage of the jfet

sir ur videos are soo gud plss upload depletion and enhancement MOSFET videos along with their characteristics plss sir I have an exam tomorrow

It was very nice explanation thanks u sir

Amazing lecturesss

As Drain current is maximum when vgs= 0, we can also see that by increasing more vgs value in +ve side there will be no effect of it on id but if we increase in negative then it may affect that's why.

Thanks a lot for the explanation sir...I have exams around the corner and this has helped me a lot..and HOMEWORK:If we increase the Vgs value to +ve, the pn junction between gate and source becomes forward biased and the depletion layer decreases and as a result the current flows towards gate resulting in damage of the device...

thank you soo much sir !

I think when we apply Vgs+ than the VGs will forward bias and depletion reg ion become less and less and cause more voltage drop across drop to source so will increase current producing more heat and than the circuit will burn out

Nice video Thank you friend

Very helpful.. Thanku g

Thank you so much sir

Thnx for your work I love it Btw on a different note I was wondering what app you're using in the video

in N ch. if VGS>>0 depletion layer will not exist because it is like a forward bias PN junction, the JFET is short circuit, current will flow on its maximum

Thanks a lot sir🙏🙏

Superb👌👌

siR YOU said Id=constant only in case of vgs

For Vgs becomming positive the circuit becomes forward bias and thus depletion region would get narrow and thus no pinch off voltage condition would occur.

when vgs>0 then the depletion region would decrease which can make pn junction to forward bias on further increase , no pinch off occurs.

if we make vgs positive it will frwd bias the gate source junction and the current will flow through it and as their will be no pinch off voltage developed it cannot be used as constant current source

if the value of Vgs is increased to such a level that the potential exceeds that of n channel( or VDS) then there will be a forward bias and the depletion layer will decrease and hence the jfet will never behave like a switch because pinch off condition will not be achieved.

as vgs increases the width of depletion layer decrease for particular value of vds so vds should be increased to reach pinch off voltage and hence ohmic region increases

If we increase the positive value of the gate voltage in the n-channel JFET, the depletion width will decease and the conductivity of the channel can not be controlled any more...

How is vp

In my opinion if Vgs is made positive then value of Ids obtained will be with infinite slope or very large value. Within the ohmic range

If we give a positive voltage to gate the depletion region in the gate is small so we have to give more and more voltage(VDS) to attain a pinch off voltage and to get a saturation current .

on making Vgs more positive then p n junction will be forward biased due to that electrons from source will not further go to the drain but will go to gate terminal.

Legends know that he will explain it in his next vd...

If we make Vgs >>0 , we will need very high Vds to make the pn junction reverse bias , hence we will get pinch off voltage late .

Sir , as you said that when Vds=Vp then Id becomes constant so Vp has some positive value from there but you take Vp =-4V what does it mean?

if we connect the vgs as +potential then it is in forward bias and no depletion region form

if vgs increases the deplection layer will be narrowed down current id will not be constant and id will increase

When vgs is positive the transistor will operate in forward bias and in forward bias there is less depletion region so we cannot fin pinch off at lower value of vds

the pinch off voltage is negative hence we need to apply vgs as -ve only (depends on vp)

Thanks

thanks for your videos Sir but I have a doubt why we have taken pinch off voltage negative Vp = -4V. Pinch off voltage is that corresponding Vds in which Id is constant(Idss) and Vds is positive. then why we have taken pinch off voltage negative.

In an n-channel Junction Field-Effect Transistor (JFET), increasing the gate-to-source voltage (Vgs) has a significant effect on its operation. Here's a general overview of the effects observed when increasing Vgs in an n-channel JFET: 1. Increase in Drain Current (Id): As Vgs is increased, the channel between the source and drain becomes more conductive, resulting in an increase in the drain current. The relationship between Vgs and Id is typically linear, following Ohm's Law. 2. Decrease in Channel Resistance (Rd): The increase in Vgs causes a larger portion of the channel to be depleted of majority carriers (electrons in the case of an n-channel JFET). This depletion region reduces the channel's effective length, leading to a decrease in channel resistance. Consequently, the JFET behaves as a lower resistance device. 3. Widening of the Depletion Region: With increasing Vgs, the depletion region at the pn-junction between the gate and the channel expands. This expansion narrows the channel's effective width, resulting in a reduction of the available conducting area. As a consequence, the channel resistance decreases. 4. Saturation Region: Beyond a certain Vgs value, known as the pinch-off voltage (Vp), the JFET enters the saturation region. In this region, the channel is fully depleted, and further increasing Vgs has little effect on Id. The JFET operates in a cutoff mode where the drain current remains relatively constant. The reason behind these effects can be explained by the underlying physics of the JFET: The n-channel JFET consists of a thin, lightly doped channel region with p-type material on both sides (the gate and the substrate). When a negative voltage (Vgs) is applied to the gate with respect to the source, the pn-junction between the gate and the channel becomes reverse-biased. The reverse bias creates a depletion region in the channel, devoid of majority carriers. As Vgs increases, the electric field at the pn-junction strengthens, widening the depletion region and reducing the effective channel width. This depletion region acts as a barrier to the flow of current, increasing the channel resistance. When Vgs exceeds Vp, the depletion region expands enough to constrict the channel entirely, leading to pinch-off. At this point, the JFET is saturated, and further increases in Vgs have minimal impact on Id. It's worth noting that the specific characteristics of a JFET, such as Vp, Idss (drain current at Vgs = 0), and transconductance (gm), vary depending on the device's design and parameters. Overall, by manipulating Vgs in an n-channel JFET, it's possible to control the device's conductivity, resistance, and operating region, making it a versatile component in electronic circuits.

If we increase Vgs, then the reverse bias will reduce and current will increase. Id (drain current) will reach a maximum value which is called Idss (maximum drain current)

if positive Vgs applied to n channel JFET, then pn junction becomes forward biased due to which there will be the reduction in width of the depletion region, hence we then have no controlled on drain current Id, the drain current increases rapidly, hence after some point breakdown of transistor will occur, if we add more and more positive voltage Vgs.

On making Vgs positive the Gate terminal will be at higher potential as compared to source and this make the junction forward biased and the depletion region will decrease and as a result the current Id will flow rapidly and there will be no saturation of drain current

Answer to the question , It is essential that the Gate voltage is never positive since if it is so, all the channel current will flow to the Gate and not to the Source, and it results in damage to the JFET.

assume vds =0 and vgs is some positive value the two p-type have positive value compared to n-channel so pn junction will be forward biased and act as forward diode with diode characteristics as vgs is slightly increased ig will increase rapidly

if we take Vgs as +ve then p-type material will become +ve & n cannel already at +ve potential..so deplation layer will not be elongated ..as i thought.

If we put +ve Vgs then the junction will be forward biased and depletion region become thin and e- can cross the depletion region and make a complete circuit to flow the current .hence we find the lass value of drain current .Now we have to increase Vds more than Vdd.

When we make Vgs more and more positive in n type JFET. The depletion regions will not extend and we will not achieve pinch off voltage.

because gate is directly connected to p type and if gate to source voltage is make positive it makes the pn junction forward biased, which is abnormal case

Sir the Vp is plotted in the first quadrant but you have given it the value -4 V. How is that possible.? Could you please explain?

Sir also please include Power MOSFET ... thank you

if we takes positive bias applied between gate and source. there will no diplition layer across the channel.thus the drain current will increase. and it will considered as ohmic resistance.

if we take Vgs as positive(+ve) in case of n-channel JFET then the reversed biased condition will not be going to happen positive value of Vgs will make it forward bias and because of that pinch-off voltage will not be obtained thus the decrement in the depletion layer will take place.

First depletion layer increase but short after it becomes grater then vds it will become forward bias and current start flowing through it

If we increase the gate source voltage to a positive value then the junction will become forward bias and hence holes will also start flowing which will voilate the nature of jfet

Sir because in the previous presentation we are discussed that in case-2 Vd'd

If we make VGs more positive,we have to required further more value of Vdd to obtaining Vp

sir if we increase vds more +ve it may breakdown the junction so we increase Vgs

if we make vgs +ve in n- channel jfet then p-n junction which is previously reverse biased will now become forward biased and then depletion layer will not increase further but instead this layer will start reducing and ic will never saturates ..it will always increase

tq sir

if we use Vgs >>0V , PN junction of N- channel has forward bias course of that deflation region not create. So we can't apply greater then 0V on Vgs.

Thanks:)

great

If Vgs is +Ve then it is in forward bias depletion layer decreases Id current never saturates because no increase in depletion region.If Vgs is -Ve then it is in reverse bias depletion region it offers resistance to flow of current Vgs is more -Ve then depletion region is more and Id current is very less (in ideal=0) but in practical current is due to minority carriers .

awesome

if we make gate terminal positive we require more amount drain to source voltage propotionally ,so its difficult to achive cut off region

Amazing teaching method sir 🥰... But please increase volume

If we are applying more negative voltage 2 pn juctions are in reverse bias in that case only Vds is >0v if Vgs is positive then Vgs is < 0v in that case 2 pn junctions are in positive.

while increasing the positive potential it makes jfet gate terminal reversebias and makes less current to flow (simply acts like insulator)

please upload the video of power amplifier

If we increase Vgs more than 0V that is more positive then the the gate will be at higher potential and the Vds become at lower potential which leads to the forward biasing and there by reducing the width of depletion region

To control the output conventional current,the gate- source voltage is always negative . If we give positive voltage to gate then there will be flow of current through gate instead of flow in drain which damage our device . Ok sir thank you☺.

If we make gate to source voltage positive then heavy current will flow which can damage the transistor

If we make the Vgs positive then in further cases it won't be reverse biased and hence, the depletion layer will get smaller and thus we will never get the pinch-off voltage.

If Vgs>>0,then, depletion layer will get decreased and the pinch off condition doesnt occur,the break down of transistor will also not take place,hence,the JFET acts as a ohmic conductor.

7:47 if Vgs is +ve the current will not flow because it will more increase the depletion region

If we increase Vgs to positive value, then gate source junction willl become forward bias. As a result the electrons will cross the depletion region, which is not desired.

Sir, your explanation really helped me for my examination. Please upload the rest of the videos as soon as possible.

Because the voltage across G and S terminal is reversed bias that means it have high input impedance 7:43

If we take Vgs as positive in this case PN junction will acts like as forward pn junction diode in this case depletion layer will decrease

when we make the VGs more positive the diode will become forward bias... and all things in reversed bias will disappear , the( depletion region , IDSS etc ....) .

The ans is because this is n chanel jfet and in n type we need to make the gate terminal in revere bias if we make the gate voltage positive so gate terminal will forward bias and if we increaser the voltage more then it goes to breakdown