Raspberry Pi RP2350 vs RP2040: Performance and Power including Arm Cortex-M33 vs Hazard RISC-V 

Haha any time I have a percent sign in my script I know I'll screw *something* up!

The M-33 ARM cores in the 2350 are rather old, very simple cores that lack the features that accelerate the faster cores. For example, there is not instruction cache, no data cache, no out-of-order execution and so on. Take all that trickery out and you will get comparable performance.

@@TheEulerID Instruction cache, data cache or out-of-order execution are all general concepts that are ISA independent (well, mostly; ooo can be a pain with some ISAs). Put "all that trickery" into both and you again have a similar performance.

@@petrkubena Yes, but the difference is that such features are way more developed on the more advanced ARM cores than what is available on the RISC-V as it takes a lot more development effort. If all you are doing is comparing stripped-down RISC cores designed for use as microcontrollers, then providing the ISA designers have done their jobs right, then you will tend to get very similar results. So, the OP was surprised by the similarity in performance. It should be the other way around; if there had been a significant difference i performance, then that would have been more surprising.

Hmmm... You got me worried now... I hope I haven't expressed it wrong. I am working with this definition: If something is "50% faster," it means that the time it takes to complete a task or action is reduced by 50% compared to the original time. For example, if a task originally took 10 minutes to complete, and now it is 50% faster, the new time would be 5 minutes (50% of 10 minutes is 5 minutes, so 10 - 5 = 5 minutes). So in summary, if something completes in 50% of the time, it means it is 2 times faster or can complete the same task in half the original time.

You are right.

Who is "you", me or the OP?

You cant say, that 400 F is twice as hot as 200 C, because it is from different worlds. If something is twice as fast, it needs only half of the time.

@@GaryExplains It takes 50% of the time but its 100% faster

Yes, that video is coming soon.

@@GaryExplains You just made my day! I struggled to use the RP2040 for DSP work, but the announcement of the RP2350 with FPU support has me stoked!!

Sorry for the delay, all the code is now uploaded: github.com/garyexplains/examples/tree/master/rp2350

You and me both!

It makes me suspect that actually there's no two separate cores but one hybrid core with common ALU and separated decode stages. And this is the reason why 4 cores are impossible to run simultaneously.

They are not hybrid cores, that is plain. 4 cores need all the plumbing and infrastructure to run simultaneously, it only has that for 2 cores.

@@user-cs8qq5vt4v I was thinking that too, especially with the power usage being identical. However looking at the spec sheet they are Hazzard3 cores and fully independent from the M33 cores. They just multiplex the busses

@@user-cs8qq5vt4v you don't have to suspect anything, you can read the source code for the RISC-V cores and satisfy yourself that it is its own wholly independent design.

@@user-cs8qq5vt4vwe have the source code for the RISCV cores available. We also know m33 is a very specific ARM CPU. They wouldn’t allow a hybrid anyway (ARM is fighting RISCV hard), but even if they did grant an expensive custom license, they wouldn’t allow Pi to dilute the branding of their cores.

If you mean Arm vs RISC-V in general, I already have a video about that.

I've seen postings from RPi engineers saying it's fixed

I will likely do another video about the special features like the hardware SHA256 and the FPU. 👍

Only the arm cores, have a fpu. The Hazard3, is calculating with an abacus.

The floating point unit is my interest as well, as my current Pico project has some floating point math. I’m waiting for my Pico 2 to arrive. Thanks for the video, Gary!

The RP2040 uses the Cortex-M0+ but the RP2350 uses the Cortex-M33. The latter gives more performance per clock cycle.

I plan to do another video about the special features like the hardware SHA256 and the FPU. 👍

@@GaryExplains thank you, looking forward to it!

Yes, correct. I will likely do another video about the special features like the hardware SHA256 and the FPU.

@@GaryExplains Decoding MP3, probably needs the fpu heavily?

Neither the Arm Cortex-M33 or the Hazard3 have something like SSE2, these are microcontrollers not general purpose application processors.

Thanks. Yes, I have a GitHub repo, as I mentioned in the video. Just Google for "garyexplains GitHub" and you will find it 👍

The RP2040 had a special divider circuit that the Raspberry Pi engineers added to the chip, it was actually quite good at integer division. See www.raspberrypi.com/documentation/pico-sdk/hardware.html#hardware_divider The Cortex-M33 and the Hazard3 both have integer division built-in.

@@GaryExplains Interesting. Thanks. I'm a bit surprised by this sentence, there: "On RP2350 there is no hardware divider, and the functions are implemented in software". I'm also having trouble working out if it's possible to make efficient use of, say, a 16 bit divider to do 64 bit arithmetic and wondering how many bits that one does in one operation. The part that says "The divider calculates the quotient / and remainder % of this division over the next 8 cycles," suggests 8 bits, to me. I once wrote an integer division routine for a Z80. I forget a lot of the details but it had to loop for each bit, doing long division (quite simple, because it's binary) so the time taken was proportional to the number of bits allowed for. I expect a hardware method still has the same limitations, but just does it quicker.

What that sentence means is that the RP2350 doesn't have the bespoke divider added to the first chip because the CPUs have instructions for integer division.

@@GaryExplains Okay. Thanks.

Which tests do use the FPU a lot? Only the M33 has the FPU.

Indeed. I added RU-vid corrections 2 days ago.

🎁

@@GaryExplains Thank you!