Finally, I can understand what Mumbo Jumbo is talking about when he says: "Just connect a D-FlipFlop to a falling edge monostable circuit"" while building a pumpkin farm
Mumbo Jumbo is a Minecraft youtuber. He mostly builds the so called "redstone" contraptions, which is basically a implementation of basic circuit elements inside the game. There are some people who made entire 8-Bit computers inside Minecraft
This reminds me on a project of years ago. It was used to create a audio echo with using serial shift registers. They called it a bucket line storage and used 8 bit wide and 1k long registers. The delay with running through those registers produced an echo effect.
thank you so much sir.the lecture was really helpful.can u please upload ur lectures on SIPO,PISO,PIPO,universal shift register,biderectional shift registers and buffer registers..it would really be of great help.
Thanku thanku sir, this is such a best teaching style. This helps me a lot. ur teaching style is amazing, .. please provide lecture on multi vivrational circuit.
@Prateek Patel I am guessing because of the clock it will only take the value that is current. For example when d3 receives a input and d2 will also receive a input at the same time because its a synchronous circuit so at that when d3=1, q3 has a previous 0 which transfers over to d2
First of all thnx sir.I am a student of IITI and your videos were of great help.The way you explained each topic with simplicity and to the point was great. Keep it on and thank you very much.
Thank u so much. Looks very simple when u teach.. Please make some more videos on ...minimization of specified sequential machines,partition techniques and merger chart methods-concept and minimum covertable.ASM- ssynthesis of output and state functions, data path,control path partition based designFault detection and locationI have seen almost all of ur videos of digital electronics and I bet no one can teach better than u. Pls pls make some more as soon as possible my exams are very near or provide me some good links.Thanku !
CONFUSION......3:09 you have said that "I have already written the outputs before giving the inputs which are 0,0,0,0". Now when input was given to D3 ie D3=1, even after that you have taken D2=0 as Q3 was equal to 0, but you have given input 1 then Q3 would be equal to 1.....plz explain it
good presentation of the concept thanks for the input., and finally learnt the meaning behind the concept of connecting a D-flip flop to a falling a edge monostable circuit cuz ot has been a pain to understand the fundamentals behind it for the last 2 months for me! great vid!!
9:31 but to get the entire output of 1111 shifted out we would need eight clock pulses right? Because we can only see Q0 as the output then after 4 clock pulses the o/p would be 1 but as we go from 4 to 8 pulses we would get 1,1,1,1 as the o/p of Q0.
🙏🙏🙏Thanks a lot sir🙏🙏🙏 Your videos are so helpful and useful during my university , I can't understand in online lecture and I don't attend it but I see Your all videos to study and I pass with good marks in my sem 3 university exam which is offline its because Your youtube channel and your extraaudinary teaching . Thanks a lot for making this videos and giving precious time us. -Thanks a lot -God bless you ..sir -I don't have words to express thankfullness to you Your youtube channel is an individual university. Thanks a lot for helping us 🙏🙏🙏🙏🙏
maybe because it is negative edge triggered flip flops that we are using, so the q3 changes only at the negative edge since Din=1 but at the time of clock change q3 is still 0 so there's no reason for the q2 to change as q3 changes just after the clock change
Because it is negative edge triggered not negative level triggered. So D2 has to wait for the negative negative edge to change its value. What I meant is that value of D2 won't change until the next clk pulse.
Well it's because of clock and I its think already explained by people below but keep in mind that dont state the reason of d2 to being 0 by stating that clk is negative edges/level triggered in exams because you can keep it positive as well , would work just the same but the graph would differ .
Thanks for the explanation but I have a question. Do we really need only N clocks for an N bit SISO register? Since we are tapping the output only at the end. Someone help me understand better
thaaaaank you very very very very very very very very very very very very very very very very very very very very very very mmuuuch , I got an " A " and you course was helpful
I was wondering when D(3) is 1 Then Q(3) is 1 , then why (D2) is not equal to 1 and that results in Q(2) is equal to 1 and similarly (Q0) is equal to 1 instantenously as these are all are connected?? why the value of Q2 or Q1 or Q0 changes only when second or third is provided to D3.
This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases. Hope this helps.
Thank you so much for clarification, I did thought may be it was because of master slave relation where on first it gets stored and on second pulse it shift. How wrong I was and I asked the same thing to many my friends but now I realize they have all wrong concept of it. Now it solves all and fit perfectly to puzzle. And By the way thank you so much for such nice lessons..It has helped to an enormous extent, whenever Teacher teache us and I have no idea what he is teaching....your channel always comes in my mind and take away all worries and when I came back you don't disappoint me too....Thanks one again.
I need to know how to solve this kind of problems as soon as possible Sir, - You have an 8 GB RAM module with 8 byte words. Calculate: The number of locations in the RAM module. The number of address lines in the RAM module. - Given that the RAM is constructed from 4K X 16 bit RAM chips, calculate: The number of chips needed. The number of address lines that need to be connected to the 4K X 16 RAM chips. The number of address lines that need to be connected to the decoder. The size of the decoder required.
In case you have nt got the ans., still.....That is Din as in the input , in the subsequent lecture he had told that its a good practice to raise it before the negative edge just for the initial inputs(not for Q0, Q1, Q2, Q3) .That is how the system literally works.
