Snooping-based Cache Coherency Protocol 

Clear and great! Really help me a lot! Thans for sharing this video!

Really, Cool Presentation.

great explanations!

Very clear and nice explanation. Thanks a lot!

Nice presentation! May I know what write strategy does Intel and AMD use? Write invalid or Write update?

At 3'31'', what will happen if p1 and p3 set the cache line at the same time?

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One point seems questionable. Why p1 is in initial, cache read miss, it send one snoop read to peer. But no peers have this address, it read the data from main memory. Then put it status to share? Does it should be in Exclusive is better?