STM32 Fanout: Through-Holes vs. HDI

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Tech Consultant Zach Peterson explores an STM32 that comes in a fine-pitch BGA package. He shows how to fan out the BGA using either through-hole layers or HDI layers.
0:00 Intro
0:38 Predicting Signal Layers
6:30 Through-Hole Vias Method
11:05 Blind & Buried Vias Method
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Опубликовано:

24 июл 2024

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Комментарии : 15

@ultrarichie 10 месяцев назад

this is a good drill for designers to get familiar with those types of technologies. as always, thank you Zach

@wyattr7982 10 месяцев назад

I started working on some BGA breakout stuff yesterday, perfect timing!

@km-electronics1 10 месяцев назад

Thank you so much for sharing this.

@deangreenhough3479 10 месяцев назад

Thanks Zach :-)

@rodhoffman 10 месяцев назад

Hi Zach, this is a great video and much appreciated to show patterns for how to fan out small pitch BGA. Out of curiosity, the aerospace world in my experience has always been wary about the use of BGA components with pitch less than 1.0mm. I'm assuming this has something to do with the reliability of the actual physical implementation for building blind/buried vias and I tend to recall a rule of thumb of only utilizing board manufacturing houses that utilize mechanically drilled holes instead of laser technology. Do you have any insights or other thoughts on this topic where boards are required to maintain high reliability after running through extreme thermal shock cycles while also employing the use of tight BGA grid pitch dimensions? Could that potentially be more related to surface tension and curvature on the board itself with potential to crack or 'pop off' leads of a BGA component?

@r4yguzman190 10 месяцев назад

Hi Zach and Altium Academy, please a video or videos on spice simulations on Altium for rookies I'm a EE student and new in the world of pcb design and i would like to learn about simulations

@Sardar-usa 8 месяцев назад

I would like if you give some information ipc requirements for class 3 and class 2 pcb. Like conductor thickness, through hole, blind via , burried via copper thickness.

@thomasyunghans1876 9 месяцев назад

Hi Zach, You added two layers to your 6 layer board, but you need 6 of them to route out the bga. That only leaves two layers for power and ground to separate the signal layers to avoid layer to layer crosstalk. Are you concerned about that?

@Zachariah-Peterson 9 месяцев назад

I'm not advocating that you only do this on 8 layers, just showing that you only need 6 of them for routing signal, I only added the two extra layers as an example. More layers would be needed overall to use this component and other components on the PCB, and some of those layers would be GND/PWR or other SIG layers for other devices.

@stevenm8393 9 месяцев назад

Thanks! Moving to a 0.5mm pitch, is it just more aggressive trace sizes?

@Zachariah-Peterson 9 месяцев назад

It is not necessarily more aggresive trace sizes unless you are trying to route between pads in the BGA footprint. In small pitches like 0.5 mm or smaller you might find that you cannot get traces between those pads due to the small clearances allowed between the pads unless you use an additive process for fabrication. Really what you will need to do is eventually get down to minimum mechanical drill size and do everything with blind/buried vias in i + N + i stackup, and you still might not be able to route between the pads even on inner layers.

@stevenm8393 9 месяцев назад

(I'm a junior EE supporting the other EE's so bear with me) This is our first 0.5mm bga. We're doing a combination of thin trace sizes (2.5mil at lowest) with a i+N+i arrangement. A problem we're facing are microvias opening at temperature, either during population or our temp cycling. From our fab houses to online documents, the third stacked microvia is mainly what causes issues. Are mechanical drills even an option at this size? I thought we needed lasered vias. Trying to stay away from VIP. Cost isn't really a factor, we just need these boards reliably made. I'll have to take a look at the additive process you mentioned. Thank you again, your videos teach me so much.

@ostrov11 9 месяцев назад

... не забудь позвоните Маме ))

@monkev1199 2 месяца назад

I dont think this video considers the ST part shown there actually has a large ground area and power area in the middle. So really 10 layers isnt needed.

@Zachariah-Peterson 2 месяца назад

It's been awhile since I did this video.... as I recall the STM guidance stated 6 SIG layers, not 10, but that higher layer count would only come from interleaving between all signal layers in that fanout regardless of whether there is a cluster of signal or ground. That's what would be needed assuming all the rest of the SIG layers are filled and you need all that ground everywhere. So in reality for the entire fanout and if you have not many other signals to worry about you could probably get away with 8 layers.