@@ChatGPT1111 OOoohh god bless you for asking about cats and videos because without cats what hair would we have to eat so god bless cats and hair and god bless god for making cats have hair well there are cats without hair so god bless the weirdos who bred hairless cats and the weirdos who buy them ohhhhhhhoh
yes it is amazing. universe created the most powerful object in existence and it only weighs 3 pounds and you can hold it in your hand. the human brain. we are extraordinary
I'm Brazilian, and I graduated in microelectronic processes. Only 7 people graduates in this area per year in Brazil. Later (about 10 years ago), I attended a course on chip design. I'm among the select few who had some education in microelectronics in this country. Needless to say that I never worked in the area. My diploma is gathering dust, and I actually work with software development, where I built a career out of grit and stubbornness. I like to watch your videos, to reminesce about the 5 years of my life that I wasted studying those topics, how even back then the course was hopelessly obsolete, how now my knowledge is about 50 years out of phase with current trends (It was already 30 when I was a student). It was a difficult course, with high turnover, and no hope of employment. I was a fool for going through it. At very least it was State sponsored and I paid nothing.
Semiconductor fabrication, only has industries in Asia region, particularly china taiwan korea.... unless you r in those countries, speak korean or mandarin... if not i do not foresee your country capable of producing any related job for it. Do what ur country,Brazil good at...maybe burn down amazon, be farmer or play soccer...
Yes look into jobs in for example the US. They are building lots of new fabs here in the news recently, I can only imagine people with your knowledge is highly sought after. Doesn't hurt to apply and look into.
I'm in IT and worked in a university computing science department, and this is as good an explanation of the past, present, and future of transistors as I have heard.
I became a grad student at UC Berkeley's EECS department in the Fall of 1984. Following my undergraduate degree in electrical engineering and med school, I wanted to know more about semiconductor device physics. I prepared for prelim exams with an undergrad course taught by professor Chenming Hu. He was a superb teacher and communicator. I subsequently learned he is also a superb human being. Professor Hu, if you are out there, this humble medical device scientist is great full for your teaching and the gift of putting to use the FinFET electronics to better manage heart diseases. God speed, professor.
Hey I just wanted to tell you how much I enjoy and am informed by your videos - love your choice of topics, sometimes quirky (Venera Program), sometimes highly topical (Hardware for AI) but always insightful. Your level of engagement with the physics and math hits just right for me. Congratulations and best wishes for a prosperous 2023!
Small correction: I was at a factory making military devices containing 3-D bipolar transistors and other devices, in MMIC's in the early 1980's. The difference was that they were much larger devices than the modern versions.
Everyone forgets that DARPA is often the mother of our modern invention era. They only focus on where commercial production ends up. A whole era of innovation in technology usually begins at DARPA
I cranked the volume on my headphones to force this information into my brain. Asianometry does a stupendous job of informing, what was, what is, and what's will be. Technology keeps throwing curve balls, Asianometry shows us the pitch.
Thank you for this! I had to smile when you mentioned your father at NSC...that's where I worked first...at their first fab (I don't think we called them that at the time!) in Danbury CT
Yeah which is why his non semiconductor/hardware videos has more views. Hopefully he gets paid more (cpm) for the high IQ videos which are his signature ones.
I like these videos. I am no engineer, but I understand the "problems and hurdles" with new processes and like knowing more details rather than "there are yield problems with the new technology"
Another outstanding video, great summary and great visuals. Slight correction: Intel moved to high k metal gate for 45nm. Their 32nm node was a shrink of 45nm, the second high k metal gate node, and, as you noted, final planar node. Samsung tried to squeeze one more planar process for 20nm, but it was a disaster. 14nm yielded far better with finFETs.
Very well written and paced, love the narrative! If I can make a suggestion, for those of us viewing at night or on a home projector, it would be great to show article screenshots in dark mode or at least a lower contrast background (something like the warm brown color of parchment) to reduce the sudden switching between graphics / photos / video and the full blast of a 255-255-255 bright white page of paper.
My commendations for how you manage to keep these videos both informative AND entertaining. I have no particular skills in CPU or semi-conductor architecture yet I find your videos fascinating. I'm a double STEM grad (physics/finance) so I know how tough it is to make subject matter like this appeal to specialists or students within the field, let alone casual observers like myself. Well done sir!
Thanks for that explanation, I kind of actually understood this one a bit. Like in buildings, each floor you build comes free as you pay for the lot size only once. But the higher you go the more they cost per floor. Charles
Kind of, kind of not. In architecture, each new floor costs marginally so little compared to the marginal value it adds that it makes sense to build higher. A more apt analogy is that building higher was what they did before hitting the limitations described in the video. So finfets is as if now everyone would have to build cantilever buildings or buildings with holes in them to pass wind flow, to compensate for not being able to build higher. So in my opinion examples of "finfet buildings" might be The Link in Dubai (cantilever skybridge between two buildings) or 432 Park Avenue in NYC (a very tall building in comparison to its footprint.)
Great video, saw you got 400k subscribers now too! I remember when you only had like 40k but the videos were the same high quality and well researched as they are now. Glad to see you finally get the viewers/subs this level of content really deserves
in spite of all the terrible going on in the world, its things like this that make you think that its really a great time to be alive and seeing all this happen.
Well, statistically speaking there was no better time to be alive. Never has a larger percentage of the human population lived in peace, didn't starve and so on. Problem is that nowadays you have the means to inform you about all the crap that happens anyways.
@@Noise-Bomb that is true but human brains are wired to react far stronger to threats and negative emotions than positive ones. Its a beneficial survival strategy in the wild but anachronistic in modern society
It’s nearly twenty years since I was in the semiconductor industry, your videos give me an excellent insight into modern developments. Thank you for taking the time to make them.
You do a SUPER human job of taking theese abstract concepts and making them readily available to all. I am a technologist with almost foury years in semiconductors and learn something everytime I tune into your channel. Thank you for all your hard work!
Awesome content as usual, spent 16 years in semi as equipment tech, late 90s to early 2000s started in military ceramic packaging and ended up in R&d fab dry etch, your content is fantastic thanks
Nice video, this info reminds me some words in the datasheets of some discrete power semiconductors transistors like: TrenchFET (Vishay), HexFET (Infineon-Int.Rect), SuperMesh (ST), HiperFET (IXYS) and CM2 (CREE). Some techonologies are for lowering the RDS_on and other to withstand high open voltage (some mosfet are rated to 1.7 kV OMG!)
I always thought HexFET sounded weird but didn't look it up until today. Turns out that it indeed consists of a hexagonal lattice as the name might imply. Zeptobars even has a die shot of it.
back in my school days (80's) asked my teacher why dont cars park themselves? My Teacher (Alan Bleasedale, i'll never forget you sir) replied.. "its already possible.. But it's a lot of cost. putting too much advancement into products that people cant realistically afford leaves a void. yes you a great thing, but you have no customers"
@@Palmit_ Yeah The same Fallacy present in all humanity lives there is many thing that or so called Artifacts has been created in the past that amaze us still this day but usually they only exist a few and only leader of a tribe, nation or a wealthy man in a nation with particular interest can afford it. Economic feasibility is what hold back innovations.
Executive summary: Great video! As a software person working closeto hardware I know much of the information in your video but not necessarily the background such as history or who invented what an its great to see all this information to be presente in around 15 min. Considering you also need to edit etc. these videos I'm sure you have Snowwhite's dwarves and many more minions working for you in the background ;-)
The true geneous of FinFET was it allowed scaling using traditional equipment. The next generation when likely be far to complicated and difficult to yield to be economically viable apart for millitary applications. The next evolution to home computing will be multi processor systems and a return to multi GPU architecture. As for improved efficiency we are at the end.
As developing new nodes gets more expensive, it'll just happen slower. Given time, paying for it is no question. Once the entire market has bought the last node and doesn't want more of it, the payoff for coming up with node n+1 becomes astronomical. Right now that's not the case, previous node is just a few years old, and node n+2 is coming soon enough, no problem to skip a node or few.
The smaller transistors used less power because their capacitance was lower. There was a smaller amount of energy needed to transition the gate from off to on (or vice versa). This is what has enabled computers to become more powerful whilst not using more energy.
Just want to thank you for making this content! There is not a lot of quality content on the industry I both work and am interested a lot and it's great to have something where I can say, hey I have worked on this or I have seen this or I found that interesting as well. I have shared this channel to so many customers and colleaugues I work with and shared on every unviersity or workshop lecture I gave, You are amazing! I always had the idea of starting content creation on Semicon in the back of my mind, and this is really inspiring!
Hu Chenming, born in Beijing in 1947. Grew up in Taiwan, earned a scholarship for Berkeley UC. Chinese talent saved the proud American industry. Probably for the last time.
Hopefully N2 has good yield. Unless there is a major improvment in power consumption, smaller chiplets with high yield coefficient will be needed for any significant advance in value to the end user. It has been almost 10 years since N32 and I still don't see much incentive to upgrade, as someone that had a home computer all through the '90s when 2 years without an upgrade was a long stretch,that is shocking. A decade for few more cores that I rarely need, maybe 20% boost in clock speed, AVX512, compatibility with slightly improved motherboards (PCIe and DRAM generation bump), and maybe 5% energy savings [whole machine], all for the low low price of 3 times what I paid for the n32 based machine.
Hmmmm... The way I see it, the next step is full 3d. Not merely adding 3d features to existing 2d basic structures, but outright building those structures in 3d, floating anywhere in the volume of the chip, all the way from up against the pads, to down against the substrate. If you can additively manufacture a gate, an insulator, and a channel, you can (probably) additively manufacture a source and a drain. Maybe even a structurally weak breakaway layer to save substrate. Maybe mixing sizes on a single chip for power and stuff. Added bonus: if you can stack logic on top of itself, you need less chip area for the same device size, allowing the use of smaller (and hopefully easier) photomasks (at the expense of more of them). Though it might be time to abandon photomasks altogether in favor of scanning the pattern (resin 3d printers do this exact thing at macro-scale).
At 11:32, I believe fin pitch is the distance from center to center (or side to side) of adjacent fins. The area between fins is for electrical isolation to prevent crosstalk.
The good news is that once we’ll reach the electron minimum size, they’ll be forced to optimize the software and instruction sets rather than just shrink and add more transistors.
Almost all of TSMC's customers have cut back orders for this next year. Economics is pushing costs too high and many customers aren't buying anymore. But, TSMC has been making very large profit margins as they've kept raising the price for their advanced nodes and this is why chiplet design is going to become common. Not all types of components in these ICs scale down in size past a certain point and in reference to TSMC, this happens around their 7nm node, so companies like AMD who make graphics processors and CPUs have moved a lot of the circuits that don't scale down in size onto another chiplet of a less advanced node. In the case of their new Zen 4 processors they have core chiplets that are on a 5nm node and they have a die that deals with I/O for the most part on another chip. For all modern CPUs for PC these chips get mounted onto a tiny PCB and a metal cover goes over them and that is the CPU. Something like a Zen 4 8 core CPU has 2 chiplets, one 8 core chiplet and 1 I/O chiplet (CCD and IOD) and in the case of a 12 or 16 core CPU there are two 8 core chiplets and 1 IOD. But here is where it gets interesting. TSMC and AMD have produced CPUs that have cache on a die that sits directly on top of the core chiplet and this gets called Vcache or 3D cache. There are metal conductors, like very fine wires maybe a little wider than a hair that runs between the core chiplet and the cache stacked on top of it. This came out with Zen 3 for a single part, the 5800X3D and it benefits gaming and programs that work with very large data sets, mostly in the world of scientific computing and modeling. It also came out with a line of server CPUs. While it's true that these more advanced nodes are more expensive, it's also true that TSMC is gouging its customers who can't do anything about it because TSMC is the only company making nodes like 5nm, 4nm and very soon 3nm that can ALSO clock at very high speeds. Intel is supposed to have their 4nm node ready this year and will release products on it and this puts SOME competition back into the market. Samsung as said is starting to produce 3nm, but Samsung nodes can't clock at high speeds which is critical for High Speed Compute (HPC) devices like servers, PCs and some other high speed electronics. Not a smart phone. That's not an HPC device. Those ICs are clocked a lot slower for power efficiency which is what Samsung nodes are good for. Now, how this could all play out in the future is if TSMC doesn't get the hint that they need to lower prices, a company like AMD could start making CPUs using 3nm for the core chiplets, but move L3 cache off the core chiplets ALTOGETHER and stack it over the core chiplets, using making a 6nm or 7nm process node. L3 cache is the slowest cache in a CPU so it CAN be stacked and take almost no performance penalty for doing so. So now for your cores you already have 2 different die, one stacked on top of the other, and then have the IOD for comms off the CPU and of course that IOD would remain on a 6nm node like it is now. This would make these CPUs very complex, but necessary if TSMC is going to continue to gouge its customers. And TSMC IS gouging their customers. They're making very large record profits as companies often do when they have no competition. So at the end of this video when the discussion was these nodes like 3nm may cost too much, the point is really TSMC is making it cost too much, and the same is true with their 5nm node. Nvidia is using TSMC N4 for their new line of graphics cards, the 4000 series or Ada Lovelace, same thing. Their prices have taken a large jump. AMD is also using TSMC to make their new line of 7000 series RDNA 4 GPUs, but they're using TSMC N5 and N6, where N6 is cheaper than N5, and AMD is the first company to every make a graphics processor be multiple chips, at least for the PC. AMD has moved a bit of cache onto 6nm chiplets right beside the graphics compute chiplet, and this allows AMD to keep their use of TSMC 5nm (N5) to a minimum. And TSMC N6 is really a 7nm node that's enhanced so it's priced more like their 7nm node, N7. Intel is moving to chiplets for their next line of CPUs. They've confirmed it. They also expect to use their 4nm node and also TSMC nodes together in this chiplet based CPU. I'm really interested to see this because it's going to be two big jumps in technology by Intel over the last 3 years. The first was moving to a hybrid core architecture where they use a form of big-little for their cores (big and little cores) and now they're moving to chiplets like AMD. AMD and Intel are really close to each other in compute power, with Intel having an advantage when they can get a lot of little cores (e cores) into a CPU and give it a higher core count compared to its AMD counterpart. Intel also added hardware acceleration to their CPUs. AMD will probably need to get hardware acceleration added ASAP and also move to a hybrid architecture of big-little. It allows for more thread processing in a smaller space. So yes, these nodes cost a lot but this is partly due to a TSMC money grab and this could be put in check if Intel competes with their 4nm node (in fact one customer has already left TSMC to use Intel) and ESPECIALLY if Intel gets to 2nm first, and they could. But this price gouging by TSMC has ALSO led to AMD doing some creative stuff which has also pushed Intel into doing creative stuff and the consumer is better off because of what happened but now we all need TSMC to drop their prices.
HPC doesn't use high frequency. The fastest computer in the world clocks at 2GHz. GPUs are increasingly important in that space and they clock even lower.
@@grizzomble They run as fast as they can. Their limitation is power consumption. When a CPU runs that slow it's usually because it has to fit within a certain power budget. The Frontier supercomputer made with AMD graphics and EPYC CPUs have 64 core CPUs in it. The BASE clock is 2GHz. Yeah, it's 64 cores in a single package. This is for power efficiency. But its BOOST clock 3.5GHz I'm pretty sure that boost clocks aren't disabled in that system. However HPC is MANY systems around the world and I generally meant that for any device that can be used for complex computing which also means PCs, AND by definition PCs CAN be part of an HPC configuration because compute can be distributed. So, for every ONE system that might be restricted in clock speed there are at least 10,000 that aren't. It's a silly point because this video is really about this very topic really, because node shrinks are for two reasons, power reduction and improving transistor density, and companies take advantage of both. Back in the olden days when even a server CPU only had 8 cores or less, those CPUs were clocked as fast as possible and in fact that's what partially made a server CPU, higher clock speeds and more power consumption, but a switch happened when process nodes allowed server CPU to start including 16+ cores in them, to where you COULDN'T clock them as fast as possible because the power consumption would be too great in a single package. So what does HPC use? Whatever it can.
While packing more transistors in a small space is already happening, clubbing quantum computing with it will add a new dimension to extreme computing chips in the near future. Imagine every nano chip is a super computer with terabytes of memory!
This is really the key issue. If cost/transistor stops declining, ever smaller nodes will become increasingly niche. You will get more bang for the buck by just stacking 28nm chips. For everything other than the most power constrained devices, it would make little sense to go below 28nm.
“By 2020, there will be chips everywhere because chips will cost a penny. After 2020, it will be the post-silicon era, with quantum computing.” This is how theoretical physicist and futurist Michio Kaku opened his speech. Ah, I miss the good old days of optimism
@@karimchaffai5922 "Moore's second law, says that the cost of a semiconductor chip fabrication plant doubles every four years. As of 2015, the price had already reached about 14 billion US dollars." -- Wiki
Protean transistors where each gate is a protean? Genetic engineering industry could help with that. Protean folding comprehensions has made a recent giant leap. Our cells use proteins like machines. We can use proteins like electronic circuits.
Interesting to think they can make such complicated 3D structures using lithographic methods. One kind of wonders if this kind of technology would allow for some other potential things as well in due time. To bad the cost is only going up these days though, I guess they will have to find a way to reduce costs in future or accept things starting to slow down once more. Maybe some kind of self assembly technology could help here? Or will it be yet another extra cost? Well I guess we'll find out.
With the last litography when you have multiple channels per gate... you can't control those channels individually then, right? What are the applications of that?
My thoughts on this are in the 90s it was already clear we see the end and I was still a pupil but one way I saw was 3D CPus . Yes I know like he said they are already do some more layers on the CPU/GPU these days but you can't go far with this because you trap the heat inside with this. I watched a video on youtube about a different type of transistors which solve this by not blocking the current but just switch over basically you have 2 inputs and 2 outputs with something like this it would be possible. The down side like he said such a unit would have 100th if not 1000th of layers basically ^3 the amount of transistors but even more the costs . This is not a consumer product.
I wonder if there's any economic sense in back-porting GAAFETs to larger nodes like 28nm. Maybe something like SRAM density could be increased enough to open up new use cases on those processes.
Why not just make the gate as a slab to begin with, burn a couple of holes in the middle, put the gates in place, then thread through the holes via soldering, alternatively they can thread through the holes before placing the gates then grab the other end that's dangling and put it in place
You are aware of the gate width is only 5 molecules wide. This is a limit in many senses: economics, yield rate, heat generated, gate leakage, errors compounding, etc. The yield would be practically zero when the gate width is reduced to 3 molecules. As the transistor number climbs, so does heat generation and subsequent current leakage. The average audience here don't have a clue what we are facing. Dreaming about sub-nano chips would certainly be a pipe dream.
You mean gate oxide layer thickness. I don't think the gate width dimension is that small. I have the same thought of this end to Moore's law for the last 10+ years, and they kept able to improve. One way to think of it is that the amount they have to shrink and reduce is also getting smaller and smaller. But I agree, it should not be possible or significant to shrink at some point.
What next? lasers. Photonic Transistors. Sub-nanometer gates with superpositioned source and sink, and Schrodinger's insulating layer. AI will need to design it.
I have a question that many of your recent videos have got me thinking about. So 28nm is this big deal, and the "chip shortage" was all because for a whole bunch of applications (cars, military) smaller node size isn't actually desirable, but the economics has pushed everyone into the smaller node size because those are the chips that make the money (CPUs, graphics cards, AI). But what can you actually do with 28nm beyond the applications that specifically require it? Like if in an alternate universe we stopped reducing node sizes at 28nm and focused on improvements in layout from that point on, how fast would a rich gamer's beast be? What would a smartphone be able to do? Memory, storage, networking, etc.. How much are we non-AI builders getting out of smaller node sizes?
I really enjoy these videos. Can I ask if you have thought about doing a video on the rapid development of SerDes for semiconductors. As we continue to move bigger and bigger amounts of data we are going to need better solutions to move data as quickly as possible. I have been reading a lot about a company called Alphawave IP recently who do some really interesting and work were founded by ex intel employees.
