NUMA can kill your performance without you noticing it. If you are really serious about memory performance you either go HBM or design it yourself with FPGA like they do it in Military, Telco applications.
Thanks for the fantastic video! Is there a way to experiment this stuff in our RAM? I mean, creating a fragmented memory or continuous and see the difference?
Question @2:00 timestamp. No, there is no additional cost. That's the magic of virtual memory (and paging)! The processes assume contiguous memory chunk is available but internally OS maps different pages to different physical addresses.
Hello, I’d like to confirm that the referenced TLD is actually TLS (Thread-local storage)? I looked up TLD and I got Top-Level Domain in domain name structure. Thanks for your videos.
I may have an answer to your question on whether physical memory fragmentation causes a performance penalty, but I'm not an expert by any means on memory or backend applications, so expect potential mistakes in this calculation. You've said yourself that a memory page is typically 4KiB in size, so the MMU can only cause physical memory fragmentation at 4KiB borders. Which implies that within a single page the physical memory must be contiguous. The wikipedia article "Synchronous dynamic random-access memory" states: > For reference, a row of a 1 Gbit[6] DDR3 device is 2,048 bits wide [...] Assuming your system is equipped with that particular 1Gbit DDR3 memory module, to read an entire 4KiB page you would already need to activate 2 physical rows in your memory. And to read the next page you would need to activate a different row anyway, so physical fragmentation should not matter at all. What I'm unsure of is how to extrapolate this example onto DDR5, as with its introduction we switched from a single 64-bit memory channel per DIMM to two 32-bit memory channels, and a prefetch (= row) buffer size of 8n for DDR3 to 8n or 16n, whatever that n means I am unsure of. If modern DDR5 chips do have row size larger than 4KiB, as you stated in the order of 16Kib, we could now be running into that particular problem, but I've had significant difficulties getting any information on row sizes. However, I could imagine physical memory fragmentation playing a role in which bank your data will be located. From what I've understood, each bank group may operate independently of each other on activate, read and prefetch commands, but share the same data and command bus. So if physical memory fragments in just the right way, most of your data could end up on the same bank, significantly degrading performance as bank switches would need to be serialized instead of being able to operate in parallel.
