The Genius of the RISC-V Microprocessor - Erik Engheim - NDC TechTown 2021 

"Get this man some water!" yes I hear you. I am the speaker and I am sorry about this. In my defense I got a call up at my hotel literally 10 minutes before my talk, getting informed that my talk had ben rescheduled. That was the second reschedule, so not something I had been prepared for. I made a split second decision that I could run over the conference and make it on time. It was pretty bad timing for me. I was not all that awake and my throat was bad. When you see me start the talk here I have literally entered the room just 1 minute ago. So I had no time for preparation... getting cough drops, water, anti-congestion of whatever. To top it off my first HDMI to thunderbolt connection didn't work properly. I had to fiddle with that until I switched to another spare I had. So everything was just massive stress. I didn't get time to even locate the water under the table there, before I had to start. I will consider uploading an edited recording of this if there is enough interest. Hopefully I will do a similar talk in a future conference under better conditions 😉

Thanks Erik for this conference, im just learning about RISC in general, just for the fun and found your video very informative. Exciting times, one question I have is... the semiconductor shortage has been positive, negative or none of those for RISC-V? Greetings from Mexico.

is RISC-V more energy efficient than ARM?

The degree of geniusness seems to be somewhat limited.

The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles. The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems. The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems. A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not perspective for computer industry. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture: V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf): www.emodel.org.ua/en/ touch ARCHIVE, then move to 2019, then to VOL 41, NO 6(2019) pp. 77-90. This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi.

The slide at 7:39 can be quite misleading. The given die area for the A5 core and RISC-V Rocket is not a full chip, it's just the core and small L1 cache. A real chip will also have peripherals and I/O pads (little gold wires connect the external package leads or bga balls to the I/O pads on the silicon), plus higher level caches or SRAM. I/O pads are very large compared to the feature size; we're talking double to triple digit micrometers (so you could have millions of transistors on an area the size of a single pad). So even for a low end microcontroller with only 40 pins, the required area (and cost) for a full chip is more likely to be dictated by the size I/O pads than by the core itself; IC designers may end up having a much larger transistor budget than they know what to do with (I suspect this is part of the reason why dualcore MCUs have gotten relatively common now). As you pointed out, cores in desktop class chips (and really mobile phone chips too) are dwarfed by huge caches and vector registers. But the SRAM in MCUs can also be quite large. If you look up Yunsup Lee's paper on their 45nm 1.3GHz dualcore RISC-V Rocket processor, you'll see that the 1MB of SRAM is larger than both cores together. That's more than in a typical MCU, but it gives you the sense of scale. RP2040 for example has 256kB and then some, NordicSemi's nRF5340 has 512kB + 64kB. Either SRAM (for MCUs with no DRAM interface) or cache (for chips that use DRAM) is pretty much mandatory. So, even in embedded space, the core size isn't that important. In any case, we will never see a price difference that remotely resembles the chart here, because core's contribution to the size and cost of a chip is small or absolutely zero (when pad limited). There are very niche cases where the die area saving could be meaningful, however. I guess the Esperanto chips are a good example; when you need tons of simple cores with little cache and no external I/O or peripherals, a small core might indeed be lucrative.

Man this dude needs to drink some water. That said, I didn’t realise that arm processors had that many op codes. That’s not really “reduced”.

37:00 Compression and Fusion 39:00 Compressed Instructions 41:00 Macro-Operation Fusion 42:18 The Genius of the RISC-V Microprocessor would be cool if someone edited out the cough sounds before posting the video.

i love this chanel

Unwatchable. Give the man some water.

I think I just ruined my 60 minutes. The presentation is not well prepared, with very minimal explanation to the slides. The Flow of the topics is not good either. Felt like the speaker don't know much about RISC so can't actually explain the slides.

I suppose ARM should technically be a RISC processors. (Advanced RISC Machines). I got a different understanding from your video. May clarify..