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TinyTapeout multiplexer progress with Sylvain 'tnt' Munaut - part 3 

Zero To ASIC Course
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28 сен 2024

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Комментарии : 5   
@donn.website
@donn.website Год назад
Thanks for the kind words on OpenLane 2. 'twas a bumpy ride, sure, but I'm happy it all worked out 💜
@hightechsystem_
@hightechsystem_ 2 месяца назад
If the tristate buffer is so slow, I’m wondering what the result would have been of a AND at source and wide OR tree. The OR tree would act as buffers. The high latencies might make doing something like a SPI Target device hard (given read data has to be aligned against source clock, as opposed to xSPI with a source synchronous edge aligned read strobe generated by target device).
@quantumsmith371
@quantumsmith371 Год назад
Did you check the spine for antenna violations?
@smunaut
@smunaut Год назад
Because the spine is on `met4`, it's unlikely to cause an antenna violation, but to be extra sure, we have a protection diode on each input buffer wired to the spine.
@quantumsmith371
@quantumsmith371 Год назад
@@smunaut Great! Thanks for all the cool work
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