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Understanding ASICs For Network Engineers (Pete Lumbis) 

Packet Pushers
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On October 11, 2018, the Packet Pushers held their second Virtual Design Clinic. Enjoy this full-length presentation from that event.
Pete Lumbis of Cumulus Networks steps away from his Cumulus duties to share his knowledge of switching ASICs. Pete compares CPUs, GPUs, FPGAs, and ASICs.
From there, he discusses ASICs explaining pipelines, shallow vs. deep buffers, programmable ASICs, and the tradeoffs inherent in different designs.
Pete also positions various chipsets from Mellanox and Broadcom, including the Trident, Jericho, and Tomahawk families.
Register for the next Packet Pushers Virtual Design Clinic at packetpushers.net/vdc. They are free, and you won't get any follow up messages unless you opt-in to receive them.
Packet Pushers has lots of other material aimed at IT engineers & networkers. Visit packetpushers.net and subscribe to our podcast network--over 1,000 episodes in our archives, with fresh content several times per week.

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12 июл 2024

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Комментарии : 13   
@brunorijsman
@brunorijsman 5 лет назад
One of my favorite PacketPusher's presentations thus far. Well done.
@amroashram
@amroashram Год назад
I keep re-watching this video cause its full of info that needs to be understood by each network engineer , it clears a lot
@ryanmartin8954
@ryanmartin8954 4 месяца назад
Some corrections on Cisco's Cloud Scale ASICs (since that is what I primarily work with in ACI mode) - They do not use that additional ASIC to do VXLAN encap/decap with routing. That was one of the main purposes of them developing their own silicon. Only the Gen 1 N9K switches used the Broadcom dual ASIC hack. Regarding store and forward versus cut through, with the N9300 for example, it depends on speed of ingress/egress. Given it's a fabric, this makes the most sense. i.e egress interface is same speed or faster it uses cut through and if there is a CRC error, it has to "stomp" the CRC by changing the frame FCS letting other egress ports know that it has already been forwarded but it has errors. If the ingress interface is slower than egress, it defaults to store and forward. I imagine this is the opposite of what you described in relation to speed mismatch. In this case it seems they are smoothing out the difference in signal rate on egress by using the buffer. This of course is different than congestion-related speed mismatch.
@ryanmartin8954
@ryanmartin8954 4 месяца назад
As far as the different feature sets baked in (again only focused on Cisco Nexus) - Microburst detection can be useful in some situations. AFD/ETRAP/DPP are all very unique ways to work around being fair to bursty traffic as well as being fair to elephant and mice flows. As far as the gPB telemetry, I've seen a large uptick in this becoming more important. Primarily with the way this data can be used with no CPU overhead to deliver non-sampled full flow records directly to a collector. Built in tools such as Nexus Dashboard Insights can use this data beyond troubleshooting these days to do things like dependency mapping using connectivity analysis allowing you to stitch together security policy based on what's actually happening versus limited logging capabilities of these switches (they are not firewalls and are limited by control plane policing usually). The main problem with telemetry is scale of the collector and Cisco's NDI app is limited to 20,000 flows/sec.
@younwookjang6359
@younwookjang6359 4 года назад
Great presentation! thank you !!
@muzr2635
@muzr2635 2 года назад
Brilliant presentation
@iracic82
@iracic82 5 лет назад
Great job
@goutham24693
@goutham24693 Год назад
very informative talk. 👍
@compyy23
@compyy23 4 года назад
Hello, can we get the ppt of this slide too ?
@eduardocastilho6648
@eduardocastilho6648 4 года назад
Nice talk. I have a question. In a fixed-function bare metal switch, with some kind of Linux OS installed on it (ASIC not programmable), is it possible to use a CPU to process packets with headers that the ASIC is not capable of processing in the pipeline? VxLAN for example? I don't care about performance here. If so, how is it possible?
@srinivasandk9196
@srinivasandk9196 3 года назад
We could make a rule to forward such a packet to the internal CPU that can do/is programmed to do the necessary processing and feed the output modified/processed packet back to the Packet processing pipeline that can then just forward the packet on the desired output port.
@NicolasFevrier
@NicolasFevrier 5 лет назад
Nice summary, good job. (Minor typo: StrataXGS, not StrataSGX)
@StrikerL24
@StrikerL24 5 лет назад
ASICs, not ASCIs
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