Vacuum Tube Computer P.19 - Clocks! 

Thank you! I love that HP scope, even if it does weigh a ton!

Thank you so much for the suggestions! I actually managed to find a PDF of "The First Computers" and will definitely spend some time working through it!

Haha, I hope you got your studying done! Thank you for the kind words, I'm glad you're finding the videos easy to follow along with!

Thank you so much, and thanks for checking the videos out!

Also, the RC filter you have weakens the amplitude of the clock signal making that section sensitive to aging of the tube. Relying on an inductor for your delay will delay the clock signal keeping the amplitude high, in fact, if the termination and series resistor and cap load is set properly, the delay output signal amplitude will match the source signal in strength and amplitude retaining that hard digital edge feeding the G of your next stage tube inverter a full strength definitive digital edge signal.

Excellent suggestions! Honestly, inductors are black magic to me, so I tend to avoid them simply because I'm not familiar. What's interesting here though is that the lazy falling edge that's pretty apparent on the scope is actually on CL1, which doesn't have the RC delay. So, most likely that lazy falling edge is due to a bad tube or something else that I missed. As for CL2, I actually lucked out because I ended up using two inverters here to make the signal the right way round. What this means though is that the input signal strength can be pretty weak and I still get a very clean logic high and logic low due to the double amplification. But, tuning it properly with an inductor is definitely the more elegant solution than the rather brute force method I went with here, haha.

@@UsagiElectric The difference between using a resistor and inductor is that the resistor lowers the current of the signal from the source to the destination while the inductor does not lower the current, it delays the current, but, the same full signal power should make it from in to out not counting the inductor's internal resistance due to wire length. (In your circuit's case, since this will be only be something like 10ohm to 200ohm for the large values above 10000uh due to the sheer length of wire, we can call it 0.) So, when using the RC filter, you are relying that the lower current will charge the cap slower at the output. With an inductor, and just a simple restrictive load at the output, it is the function of the inductor to delay that signal without weakening it's current. This is why radios use inductors in their tuning and filter circuits. They are far more stable and pure of signal strength compared to pure RC circuits. You can take a look at finding some cheap aftermarket inductor sample kits which containing values in the 10000uh to 100uf range as all the smaller values will operate in frequencies way above what you need. You also have a good 2 channel all vacuum tube scope, when placing an inductor VS resistor cap alone circuit, you can probe the input VS output on 2 channels to see what is going on when feeding a continuous source square wave from your signal generator beginning at low frequencies like 100Hz to 100Khz range. There are many who will help you out on both the formulas of use and how to hand calculate or simulate your circuits, including with vacuum tubes at this forum here: www.eevblog.com/forum/index.php .

Thank you! I'm stupid levels of excited about this. It's been a massive project (and I'm really only about 1/4 of the way done, I've still got memory, program control and IO to tackle), but I feel like the more the processor comes together and actually starts to work, the more real the project starts to feel!

@@UsagiElectric cpu has to be the hardest part … how much RAM are you talking? Is the architecture going to be program in ram? Size of ram will i form you a lot … Yeah, lots to go yet :)

Thank you very much! I really wanted to be able to adjust it quickly and easily no matter what clock speed is coming in, and I think this setup should work pretty well!

Thank you! I've never had to remind myself to lift with my legs not my back when picking up an oscilloscope before, haha.

Thanks for checking the video out!

There is definitely a lot of tubes in the project! In total, the processor will sit at 190 tubes, which is a massive amount of tiny little heaters raising the temperature of the room!

That's a good idea! I may look into that! What really bakes my noodle though is how sharp Clock 2 is. It has two cathode follower buffers on it, but we don't see any of the laziness that we saw on Clock 1. Maybe that third buffer on the CL1 is adding a little too much capacitance or something, or perhaps I've got a bum tube in one of the buffer slots. When the tube computer gets complete, I'm going to go top to bottom and test every single tube, replacing any that don't give me the emission I want, so that may really clean up some of the signals too. Of course, here I was testing at 1kHz, and I've been thinking a lot about program control, and I'll be happy to get about 7Hz, so the lazy edge won't even be noticeable on the scope at that frequency, haha.

@@UsagiElectric Having never used tubes with a B+ lower than 150V before, It's well out of my wheel house (and I haven't touched a tube repair in over a decade.) It blew me away when I figured out you were Way Down at 24V! Do tube data charts even go that low??? A simple 10M or 22M resistor across a couple tube, from in to out might fix everything. The difference in fall times between the two clocks puzzled me also. I think a little poking around with the scope might get you a few answers. After that maybe even a couple of cathode resistors should change things... without simulations, hard to tell if it would be better or worse... but it should be more linear. (but via some local negative feedback) I though you might have to move the RC delay on clock 2 to after the first stage, (and you might try it) to clean up the problem with duty cycle. But I'm not sure on that one either.

@@idahobob Haha, yeah, just +24V for B+ is a little on the low side. Datasheets pretty much only ever give data for at minimum 50V (unless it's one of those 12V space charge tubes that were used in the 50s for cars). So, a lot of figuring out what works and doesn't was just down to trial and error to see how well things go. I did actually do some testing with cathode resistors of varying values, but I always ran into problems with logic lows being acceptable at that point. The problem was that in order to keep the cathode level low enough at full saturation, if I had a cathode resistor, I had to go extreme with the plate resistor, which meant I had to go even more extreme with the voltage divider resistors on the grid. But, with just +24V, I found that if my voltage divider resistors get too high, the grid essentially stops responding and my logic lows and logic highs only have a swing of a few volts between them. The 33k plate, 220k/220k divider to -12V on the grid seems to be a really good compromise and I get about a 20V swing between logic levels. Also, fortunately, the duty cycle problem isn't something i need to think too much about. Pretty much everything only cares about the transitions, which is quite nice. Plus, with such a low clock rate I think everything will jive together rather well. I'm hoping at least, I won't know for sure until I get some memory and program control running actual programs through it!

@@UsagiElectric LOL! I keep forgot you are doing digital. Yeah, the cathode resistors would be a huge issue. I keep coming up with "Great Ideas!(tm)" with other logic, only to realize you can't use them as you've gone all tube. So you keep going with your Good ideas! ... after all the hardest lesson to teach a new engineer is "When good enough, is Good Enough."

Thank you so much!

Thank you so much!

It totally could! The clocking really only cars about rising or falling edges, and there's really only two distinct clock operations. On CL1 falling edge, the instruction register stores the next instruction, on CL2 rising edge, IEN, OEN, and SKZ store anything if necessary, and one CL2 falling edge RR and Carry store results. So, as long as CL2's rising edge happens after CL1s falling edge, and CL2s falling edge happens before the next CL1 falling edge, it should all work alright. The main reason I did it this way was just to keep the tube count down. I knew I needed a ton of CF buffers to keep the clock signals clean and strong, so I tried to think of the simplest method to achieve the timing I needed, and this seemed to work!

Thank you! You got it, all it does is invert the data coming into the ALU to do addition on data compliment and RR. The additional 1 is added manually by forcing a 1 into the carry register, though that does require a bit of setup. If I wanted to subtract 11 - 10 = 01, this would be the program (OpCode + Data value): ONE X ADD 1 (These two operations force a 1 into the carry and leaves RR at 0) LOAD 1 SUB 0 LOAD 1 SUB 1 (Once we have the one in the carry, we just cycle our way through the operands 1 bit at a time) I really could have used to have a clear carry and force carry operation, but given I was trying to stuff all the ALU operations into just 7 opcodes, I ditched a few things to keep some logic functionality too.

@@UsagiElectric thanks for the explanation :)

Thank you so much! And I actually have seen the Gigatron (well, not in person), and I love the idea of building a TTL computer. I actually have a TTL design I've slowly been working on in the background that I want to build up someday. If it works well in the end, I want to transition the design over to discrete transistors!

@@UsagiElectric would love to see your ttl design on this channel someday

@@VandalIO That's the ultimate plan! I'm doing some simple breadboard testing now to get a feel for how it's going to be built, then, once I'm pretty happy with the overall design, I'll start making videos of the build!

I've been thinking about this too, and what's really throwing me for a loop is that CL2 doesn't have that lazy falling edge, even though it's also got two cathode followers in parallel. If it were the buffers, I feel like CL2 should be showing some laziness, but perhaps three is the magic number for enough capacitance to cause a bit of an issue. Also, I could totally have a bum tube in one of the cathode follower spots on CL1. If that's the case, it would mostly present alright because the other two buffers would be picking up the slack, but the bum tube could be causing some weird harmonics or excess capacitance that's causing the lazy edge. Although, in the end, I'm hoping for about 7Hz (roughly the speed of a reel-to-reel player), so the lazy edge is mostly a non-issue, haha.

Good catch! Fortunately, duty cycle is fairly irrelevant. As long as CL2s rising edge happens after CL1s falling, and CL2s falling edge happens before CL1s next falling edge, everything should work pretty well!

That was actually the drive behind changing from "MC14500" to "UE14500"! Though, arguably, the UE version has a bit more functionality, and I would like to actually build up a version of this on an FPGA someday to actually push it hard and see how viable of a processor it can be with a fast clock speed. I'm with you on the idea that maybe changing the digits would be more representative of the changes that were made, but sticking with 14500 feels like a proper homage to the chip that inspired the entire build!

Very keen eye! That's actually the thermal printer unit on one of the sidecars for my TI-99 setup. This is a bit of an older picture (the layout is a little different now), but you can see the entire system here: i.postimg.cc/3R89xxWy/IMAG2815.jpg

This actually comes down to how program control is going to be implemented. I haven't really mentioned it in a video yet, but I'm planning on having programs execute directly from 1/4" audio tape. Which means that each bit of the instruction word will be read in serially into a shift register, then a global clock will ping, executing that instruction. What this means though, is that there won't be an actual clock. The clock pulse will come directly from the tape (which means the clock speed of the computer is dictated by the read speed of the tape). It's going to be painfully slow, but it's kind of a necessity given how long programs will need to be to execute anything of any notable complexity.

This is a question that's well beyond my ability to answer! But, if I were to take a guess at how to do that, I would suggest perhaps looking into stuff like paint thickness detectors. They use ultrasonic sound waves and measure the time it takes for the wave to be reflected back. This of course means that the lower layer needs to be a substance that can reflect ultrasonic, so it may or may not work at all for your application, but it might be worth a shot!

@@UsagiElectric Thanks. Worth a try.

He has a discord he's really active on, check that out, I'm pretty sure he has his discord linked in some of his videos

Thanks for joining the Discord!

@@greenalien8503 Thanks for letting them know about the Discord!

Oof, that's a lot of pixel data to send 120 times a second, haha.

This explains it. ru-vid.com/video/%D0%B2%D0%B8%D0%B4%D0%B5%D0%BE-OL52f-k3iIE.html posting as a seperate comment because YT is very likely to delete this comment. 🤦‍♀

Thank you for the link! I have actually thought about it that way before. Using D Flip Flops like they explain in the video you linked is pretty common for building ring counters or Johnson counters, though the quadrature setup is new to me. It looks awesome and is something I will definitely keep in mind for the future! The primary reason I can't use it here is tube count. I've tried using my 6-tube DFF design for ring counters before, but since all the tubes I use are, well, used, I end up with really unpredictable oscillations. So, to make sure the DFF transitions properly on the rising or falling edge, I need to use a master-slave DFF, which requires about 8 tubes. So, to build the clock in quadrature would require 16 tubes, plus at least 4 more tubes for cathode follower buffers. And, I just didn't have the space for that here, though it would probably give a much cleaner and more reliable clock signal! Fortunately, the solution here should work pretty well at the extreme low clock speeds I'm thinking I'll end up at (will be dictated by program control, but my initial goal is 7Hz, or one instruction per inch and 7 inches per second).

@@UsagiElectric Thanks for you well thought out and reasoned analysis, yes, I did consider that you want the route of keeping it simple and I totally I appreciate it. I'm just one of those commenters on RU-vid that has the time to suggest alternatives, hopefully not in a toxic or unhelpful way! :-)

That's awesome! One of my long time goals is to build a 4-bit transistorized computer with core memory! I have an architecture I'm somewhat happy with, so I want to build it up as a TTL version first using 7400 series chips to work out the kinks, and then I want to tackle building it in discrete through hole transistors! Keep me updated on your project, I'd love to see more about it (and maybe steal some ideas, haha)!

I could show you a few things for my Twitter account I'm still working on it

Haha, thanks! I have a nice Siglent digital storage scope, and even a nice BK Precision analog scope from the 80s/90s (no clue on when it was actually built), but I honestly just love using the old HP more than both of those by a massive amount!