Verilog, FPGA, Serial Com: Overview + Example 

Bless you. I have lab for FPGAs but most of the time I’m doing the work myself since the TA does not know what is happening and just references the solutions. I was trying to implement this myself but for dear life could not get the timing right, which made the characters on my 16x2 LCD appear wonky. Thank you!!!

Wonderful presentation! Thank you!

Hopefully you continue this wonderful series.

gem just one of youtube's gems

Dear professor, thank you for this incredible video, just what I need to pass my Comp Arch exam in 7 hours.

Thanks, Professor, very helpful!

legend is back

thank you for sharing your knowledge

Thanks a lotttt sirrr!!

Obrigado. Os conceitos e fundamentos explicados nesse video facilita o entendimento sobre FPGA.

when do you build the riscv CPU on the FPGA ?

WOW

Thanks, Professor Harry, this is very informative, will there be more videos like this?

Excelente explicacion. Muy buen video.

great video! Thanks!

why have you taken clocks_per_bit as 543 in main module, what is the calulation of it?

awesome

where is the code in github ?

This guy hand writing is easier to read than text editor font 😂

Hi how can I contact u